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clk: qcom: gcc-sc8280xp: Use common clock controller probe data

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Move the always-on branch register offsets into a critical_cbcrs array
and describe the DFS RCGs through qcom_cc_driver_data.

Delegate always-on branch and DFS initialization to the common probe
path while retaining the device-specific setup in the driver's probe.

Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-22-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Abel Vesa 2026-09-24 15:06:34 +03:00 committed by Bjorn Andersson
parent e625772909
commit 63e284bce7
1 changed files with 20 additions and 15 deletions
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35
drivers/clk/qcom/gcc-sc8280xp.c
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@ -7509,7 +7509,27 @@ static const struct regmap_config gcc_sc8280xp_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sc8280xp_critical_cbcrs[] = {
0x26004, /* GCC_CAMERA_AHB_CLK */
0x26020, /* GCC_CAMERA_XO_CLK */
0x27004, /* GCC_DISP_AHB_CLK */
0x27028, /* GCC_DISP_XO_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
0x28004, /* GCC_VIDEO_AHB_CLK */
0x28028, /* GCC_VIDEO_XO_CLK */
0xbb004, /* GCC_DISP1_AHB_CLK */
0xbb028, /* GCC_DISP1_XO_CLK */
};
static const struct qcom_cc_driver_data gcc_sc8280xp_driver_data = {
.clk_cbcrs = gcc_sc8280xp_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sc8280xp_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
};
static const struct qcom_cc_desc gcc_sc8280xp_desc = {
.driver_data = &gcc_sc8280xp_driver_data,
.config = &gcc_sc8280xp_regmap_config,
.clks = gcc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(gcc_sc8280xp_clocks),
@ -7538,21 +7558,6 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
goto err_put_rpm;
}
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
goto err_put_rpm;
ret = qcom_cc_really_probe(&pdev->dev, &gcc_sc8280xp_desc, regmap);
if (ret)
goto err_put_rpm;