From 95b840afe420bb4152fde11473e7ce370b058c1b Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Wed, 5 Apr 2017 16:06:11 +0200 Subject: [PATCH 01/20] ARM: dts: rockchip: Setup usb vbus-supply on rk3288-rock2 Now that the rockchip usb phy has a vbus-supply property use that to control the vbus regulator on rock2. Signed-off-by: Sjoerd Simons Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-square.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index a23a94811be8..8ed25e9f60bc 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -125,10 +125,6 @@ vcc_usb_host: vcc-host-regulator { gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; - /* Always on as the rockchip usb phy doesn't have a vbus-supply - * property - */ - regulator-always-on; regulator-name = "vcc_host"; }; @@ -279,6 +275,10 @@ &usbphy { status = "okay"; }; +&usbphy1 { + vbus-supply = <&vcc_usb_host>; +}; + &usb_host0_ehci { status = "okay"; }; From 96800f036813c648cdd64918399bdd6768e68273 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 17 Mar 2017 18:18:39 +0100 Subject: [PATCH 02/20] ARM: dts: rockchip: rename core dtsi from RK1108 to RV1108 Rockchip finally named the SOC as RV1108, so change it for compatible. Signed-off-by: Andy Yan [adapt include in rk1108-evb.dts to not introduce errors] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk1108-evb.dts | 2 +- .../arm/boot/dts/{rk1108.dtsi => rv1108.dtsi} | 20 +++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) rename arch/arm/boot/dts/{rk1108.dtsi => rv1108.dtsi} (95%) diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts index 3956cff4ca79..88fe0a8c4faa 100644 --- a/arch/arm/boot/dts/rk1108-evb.dts +++ b/arch/arm/boot/dts/rk1108-evb.dts @@ -40,7 +40,7 @@ /dts-v1/; -#include "rk1108.dtsi" +#include "rv1108.dtsi" / { model = "Rockchip RK1108 Evaluation board"; diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi similarity index 95% rename from arch/arm/boot/dts/rk1108.dtsi rename to arch/arm/boot/dts/rv1108.dtsi index 1297924db6ad..437098b556eb 100644 --- a/arch/arm/boot/dts/rk1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -47,7 +47,7 @@ / { #address-cells = <1>; #size-cells = <1>; - compatible = "rockchip,rk1108"; + compatible = "rockchip,rv1108"; interrupt-parent = <&gic>; @@ -113,7 +113,7 @@ bus_intmem@10080000 { }; uart2: serial@10210000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; reg = <0x10210000 0x100>; interrupts = ; reg-shift = <2>; @@ -127,7 +127,7 @@ uart2: serial@10210000 { }; uart1: serial@10220000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; reg = <0x10220000 0x100>; interrupts = ; reg-shift = <2>; @@ -141,7 +141,7 @@ uart1: serial@10220000 { }; uart0: serial@10230000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; reg = <0x10230000 0x100>; interrupts = ; reg-shift = <2>; @@ -155,17 +155,17 @@ uart0: serial@10230000 { }; grf: syscon@10300000 { - compatible = "rockchip,rk1108-grf", "syscon"; + compatible = "rockchip,rv1108-grf", "syscon"; reg = <0x10300000 0x1000>; }; pmugrf: syscon@20060000 { - compatible = "rockchip,rk1108-pmugrf", "syscon"; + compatible = "rockchip,rv1108-pmugrf", "syscon"; reg = <0x20060000 0x1000>; }; cru: clock-controller@20200000 { - compatible = "rockchip,rk1108-cru"; + compatible = "rockchip,rv1108-cru"; reg = <0x20200000 0x1000>; rockchip,grf = <&grf>; #clock-cells = <1>; @@ -173,7 +173,7 @@ cru: clock-controller@20200000 { }; emmc: dwmmc@30110000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; @@ -185,7 +185,7 @@ emmc: dwmmc@30110000 { }; sdio: dwmmc@30120000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; @@ -197,7 +197,7 @@ sdio: dwmmc@30120000 { }; sdmmc: dwmmc@30130000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; clock-freq-min-max = <400000 100000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; From 5be21d0a0f487f779d6e1e72790852769e9d976f Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 17 Mar 2017 18:18:40 +0100 Subject: [PATCH 03/20] ARM: dts: rockchip: rename RK1108-evb to RV1108-evb Rockchip finally named the SOC as RV1108, so change it for compatible. The rk1108/rv1108 is completely new to the market, so there no real devices exist in the wild, only the Rockchip internal evaluation board. Therefore we're not breaking any existing devices when changing compatible values. Signed-off-by: Andy Yan Acked-by: Rob Herring [added paragraph about no real devices existing] Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 ++-- arch/arm/boot/dts/Makefile | 2 +- arch/arm/boot/dts/{rk1108-evb.dts => rv1108-evb.dts} | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) rename arch/arm/boot/dts/{rk1108-evb.dts => rv1108-evb.dts} (95%) diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index c965d99e86c2..7b4847420ab5 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -138,9 +138,9 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; -- Rockchip RK1108 Evaluation board +- Rockchip RV1108 Evaluation board Required root node properties: - - compatible = "rockchip,rk1108-evb", "rockchip,rk1108"; + - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - Rockchip RK3368 evb: Required root node properties: diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..32537f8c9e41 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -718,7 +718,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7794-silk.dtb \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rk1108-evb.dtb \ + rv1108-evb.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts similarity index 95% rename from arch/arm/boot/dts/rk1108-evb.dts rename to arch/arm/boot/dts/rv1108-evb.dts index 88fe0a8c4faa..58cf4ac079c3 100644 --- a/arch/arm/boot/dts/rk1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -43,8 +43,8 @@ #include "rv1108.dtsi" / { - model = "Rockchip RK1108 Evaluation board"; - compatible = "rockchip,rk1108-evb", "rockchip,rk1108"; + model = "Rockchip RV1108 Evaluation board"; + compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; memory@60000000 { device_type = "memory"; From 9d420e9b4140f8938ad6aa0d29e2428a2af6122b Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 17 May 2017 17:52:24 +0800 Subject: [PATCH 04/20] ARM: dts: rockchip: fix rk322x i2s1 pinctrl error Refer to Chapter 5.3.2 of rk3229 TRM, we can see that GPIO1A[2,4,5] using RK_FUNC_2 not RK_FUNC_1. This patch fixes it. Signed-off-by: Sugar Zhang Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 48a0c1cf4301..cc6a27dbcc29 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -621,9 +621,9 @@ i2s1_bus: i2s1-bus { <0 12 RK_FUNC_1 &pcfg_pull_none>, <0 13 RK_FUNC_1 &pcfg_pull_none>, <0 14 RK_FUNC_1 &pcfg_pull_none>, - <1 2 RK_FUNC_1 &pcfg_pull_none>, - <1 4 RK_FUNC_1 &pcfg_pull_none>, - <1 5 RK_FUNC_1 &pcfg_pull_none>; + <1 2 RK_FUNC_2 &pcfg_pull_none>, + <1 4 RK_FUNC_2 &pcfg_pull_none>, + <1 5 RK_FUNC_2 &pcfg_pull_none>; }; }; From f22e4359cd73fc335df4b13e85dbcda8bf1f25f0 Mon Sep 17 00:00:00 2001 From: Eddie Cai Date: Tue, 25 Apr 2017 14:41:09 +0800 Subject: [PATCH 05/20] clk: rockchip: add ids for camera on rk3399 we use SCLK_TESTCLKOUT1 and SCLK_TESTCLKOUT2 for camera, so add those ids. Signed-off-by: Eddie Cai Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3399-cru.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 220a60f20d3b..22cb1dfa9004 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -132,6 +132,8 @@ #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 #define SCLK_DDRC 168 +#define SCLK_TESTCLKOUT1 169 +#define SCLK_TESTCLKOUT2 170 #define DCLK_VOP0 180 #define DCLK_VOP1 181 From a1e10b50cef49145e01a0b0020864eecdcb88510 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Fri, 28 Apr 2017 15:02:46 +0800 Subject: [PATCH 06/20] clk: rockchip: add clock-ids for more rk3228 clocks This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/ VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference. Signed-off-by: Elaine Zhang Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3228-cru.h | 47 ++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index b27e2b1a65e3..56f841c22801 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -61,6 +61,17 @@ #define SCLK_MAC_TX 130 #define SCLK_MAC_PHY 131 #define SCLK_MAC_OUT 132 +#define SCLK_VDEC_CABAC 133 +#define SCLK_VDEC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_HDCP 136 +#define SCLK_HDMI_CEC 137 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_HSADC 140 +#define SCLK_WIFI 141 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 /* dclk gates */ #define DCLK_VOP 190 @@ -68,15 +79,32 @@ /* aclk gates */ #define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VPU_PRE 196 +#define ACLK_RKVDEC_PRE 197 +#define ACLK_RGA_PRE 198 +#define ACLK_IEP_PRE 199 +#define ACLK_HDCP_PRE 200 +#define ACLK_VOP_PRE 201 +#define ACLK_VPU 202 +#define ACLK_RKVDEC 203 +#define ACLK_IEP 204 +#define ACLK_RGA 205 +#define ACLK_HDCP 206 #define ACLK_PERI 210 #define ACLK_VOP 211 #define ACLK_GMAC 212 +#define ACLK_GPU 213 /* pclk gates */ #define PCLK_GPIO0 320 #define PCLK_GPIO1 321 #define PCLK_GPIO2 322 #define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_HDCP 325 +#define PCLK_EFUSE_1024 326 +#define PCLK_EFUSE_256 327 #define PCLK_GRF 329 #define PCLK_I2C0 332 #define PCLK_I2C1 333 @@ -89,6 +117,7 @@ #define PCLK_TSADC 344 #define PCLK_PWM 350 #define PCLK_TIMER 353 +#define PCLK_CPU 354 #define PCLK_PERI 363 #define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_PHY 365 @@ -104,6 +133,24 @@ #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 +#define HCLK_CPU 460 +#define HCLK_VPU_PRE 461 +#define HCLK_RKVDEC_PRE 462 +#define HCLK_VIO_PRE 463 +#define HCLK_VPU 464 +#define HCLK_RKVDEC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_HDCP_MMU 470 +#define HCLK_HOST0 471 +#define HCLK_HOST1 472 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_M_CRYPTO 476 +#define HCLK_S_CRYPTO 477 #define HCLK_PERI 478 #define CLK_NR_CLKS (HCLK_PERI + 1) From fa206984331b2fd5c8821f0ca63c8f0eec837f2b Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 17 May 2017 17:52:26 +0800 Subject: [PATCH 07/20] ARM: dts: rockchip: add watchdog device node on rk322x Add watchdog device node for rk322x SoC. Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index cc6a27dbcc29..1b46bf81932a 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -280,6 +280,14 @@ i2c3: i2c@11080000 { status = "disabled"; }; + wdt: watchdog@110a0000 { + compatible = "snps,dw-wdt"; + reg = <0x110a0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_CPU>; + status = "disabled"; + }; + pwm0: pwm@110b0000 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0000 0x10>; From 02131477b9028720037438948047a6233e8bdb81 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 17 May 2017 17:52:25 +0800 Subject: [PATCH 08/20] ARM: dts: rockchip: correct rk322x uart2 pinctrl Correct UART2 PINCTRL flag to use the correct pull up setting Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 1b46bf81932a..5300a1e765ec 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -701,7 +701,7 @@ uart1_rts: uart1-rts { uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, <1 19 RK_FUNC_2 &pcfg_pull_none>; }; From 738e451174d428881910b9b7558965668216ed5b Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 17 May 2017 17:52:25 +0800 Subject: [PATCH 09/20] ARM: dts: rockchip: add second uart2 pinctrl on rk322x Add secondary pinctrl set for UART2 which can be used to prevent conflicts with sdmmc pins. Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 5300a1e765ec..816b0796d816 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -705,6 +705,11 @@ uart2_xfer: uart2-xfer { <1 19 RK_FUNC_2 &pcfg_pull_none>; }; + uart21_xfer: uart21-xfer { + rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, + <1 9 RK_FUNC_2 &pcfg_pull_none>; + }; + uart2_cts: uart2-cts { rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; }; From 30ee58146b53d83e90fc5326488e1e48a5a3aba4 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 17 May 2017 18:16:14 +0800 Subject: [PATCH 10/20] ARM: dts: rockchip: set default rates for core clocks on rk322x Set sane default frequencies for CPLL, GPLL and some other core clocks on the rk322x. Signed-off-by: Elaine Zhang Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 816b0796d816..c256df9a2cd8 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -346,8 +346,18 @@ cru: clock-controller@110e0000 { rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru ARMCLK>, + <&cru PLL_CPLL>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>; + assigned-clock-rates = + <594000000>, <816000000>, + <500000000>, <150000000>, + <150000000>, <75000000>, + <150000000>, <150000000>, + <75000000>; }; thermal-zones { From 9f12da43c327b4eed4c7dc47a8ac37b05e39c3d0 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 17 May 2017 18:16:15 +0800 Subject: [PATCH 11/20] ARM: dts: rockchip: add operating-points-v2 for cpu on rk322x This patch adds a new opp table for cpu on rk322x SoC. Signed-off-by: Finley Xiao Signed-off-by: Frank Wang Acked-by: Viresh Kumar Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 36 +++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index c256df9a2cd8..c09e17cc4ab0 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -66,10 +66,7 @@ cpu0: cpu@f00 { compatible = "arm,cortex-a7"; reg = <0xf00>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; + operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; @@ -80,6 +77,7 @@ cpu1: cpu@f01 { compatible = "arm,cortex-a7"; reg = <0xf01>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@f02 { @@ -87,6 +85,7 @@ cpu2: cpu@f02 { compatible = "arm,cortex-a7"; reg = <0xf02>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@f03 { @@ -94,6 +93,35 @@ cpu3: cpu@f03 { compatible = "arm,cortex-a7"; reg = <0xf03>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000>; }; }; From 2b3f2f37ef4d7b9f233d7dc9529b789709b6c988 Mon Sep 17 00:00:00 2001 From: Rocky Hao Date: Wed, 17 May 2017 18:16:17 +0800 Subject: [PATCH 12/20] ARM: dts: rockchip: set a sane frequence for tsadc on rk322x Update freq of tsadc's working clock as 32768 hz, if not set, tsadc will work at a default frequence. Signed-off-by: Rocky Hao Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index c09e17cc4ab0..df574135797a 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -434,6 +434,8 @@ tsadc: tsadc@11150000 { interrupts = ; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <32768>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; From 7fa049dd1bdeb63d8beb3de6dde5a990843d0324 Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:25 +0100 Subject: [PATCH 13/20] dt-bindings: gpu: add bindings for the ARM Mali Midgard GPU The ARM Mali Midgard GPU family is present in a number of SoCs from many different vendors such as Samsung Exynos and Rockchip. Import the device tree bindings documentation from the r16p0 release of the Mali Midgard GPU kernel driver: https://developer.arm.com/-/media/Files/downloads/mali-drivers/kernel/mali-midgard-gpu/TX011-SW-99002-r16p0-00rel0.tgz Remove the copyright and GPL licence header as deemed not necessary. Redesign the "compatible" property strings to list all the Mali Midgard GPU types and add vendor specific ones. Drop the "clock-names" property as the Mali Midgard GPU uses only one clock (the driver now needs to call clk_get with NULL). Convert the "interrupt-names" property values to lower-case: "job", "mmu" and "gpu". Replace the deprecated "operating-points" optional property with "operating-points-v2". Omit the following optional properties in this initial version as they are only used in very specific cases: * snoop_enable_smc * snoop_disable_smc * jm_config * power_model * system-coherency * ipa-model Update the example accordingly to reflect all these changes, based on rk3288 mali-t760. CC: John Reitan Signed-off-by: Guillaume Tucker Tested-by: Enric Balletbo i Serra Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- .../bindings/gpu/arm,mali-midgard.txt | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt new file mode 100644 index 000000000000..d3b6e1a4713a --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -0,0 +1,86 @@ +ARM Mali Midgard GPU +==================== + +Required properties: + +- compatible : + * Must contain one of the following: + + "arm,mali-t604" + + "arm,mali-t624" + + "arm,mali-t628" + + "arm,mali-t720" + + "arm,mali-t760" + + "arm,mali-t820" + + "arm,mali-t830" + + "arm,mali-t860" + + "arm,mali-t880" + * which must be preceded by one of the following vendor specifics: + + "amlogic,meson-gxm-mali" + + "rockchip,rk3288-mali" + +- reg : Physical base address of the device and length of the register area. + +- interrupts : Contains the three IRQ lines required by Mali Midgard devices. + +- interrupt-names : Contains the names of IRQ resources in the order they were + provided in the interrupts property. Must contain: "job", "mmu", "gpu". + + +Optional properties: + +- clocks : Phandle to clock for the Mali Midgard device. + +- mali-supply : Phandle to regulator for the Mali device. Refer to + Documentation/devicetree/bindings/regulator/regulator.txt for details. + +- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/opp.txt + for details. + + +Example for a Mali-T760: + +gpu@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; + reg = <0xffa30000 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + mali-supply = <&vdd_gpu>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3288_PD_GPU>; +}; + +gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@533000000 { + opp-hz = /bits/ 64 <533000000>; + opp-microvolt = <1250000>; + }; + opp@450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-microvolt = <1150000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1125000>; + }; + opp@350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <1075000>; + }; + opp@266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <1025000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <925000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <912500>; + }; +}; From e3df026c594c77f0de1bdaa413d591b4345e4b6a Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:26 +0100 Subject: [PATCH 14/20] ARM: dts: rockchip: add ARM Mali GPU node for rk3288 Add Mali GPU device tree node for the rk3288 SoC, with devfreq opp table. Signed-off-by: Guillaume Tucker Tested-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ad5d6022e95f..2484f11761ea 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -1125,6 +1126,48 @@ hdmi_in_vopl: endpoint@1 { }; }; + gpu: mali@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; + reg = <0xffa30000 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3288_PD_GPU>; + status = "disabled"; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1200000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1250000>; + }; + }; + qos_gpu_r: qos@ffaa0000 { compatible = "syscon"; reg = <0xffaa0000 0x20>; From d6823b67288aad6810336b963140059721c83644 Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:27 +0100 Subject: [PATCH 15/20] ARM: dts: rockchip: enable ARM Mali GPU on rk3288-rock2-som Add reference to the Mali GPU device tree node on the rk3288-rock2-som platform. Tested on a Radxa Rock2 Square board. Signed-off-by: Guillaume Tucker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index f0778a46bca9..749a9b86e6e2 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -113,6 +113,11 @@ &gmac { tx_delay = <0x30>; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { status = "okay"; From 93dedf52894e360731de17bdd9358873b36c3e0f Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:28 +0100 Subject: [PATCH 16/20] ARM: dts: rockchip: enable ARM Mali GPU on rk3288-firefly Add reference to the Mali GPU device tree node on rk3288-firefly. Tested on Firefly board. Signed-off-by: Guillaume Tucker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 10793ac18599..864747342e3e 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -219,6 +219,11 @@ &gmac { status = "ok"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; From 08e779e59950affaec4f677b22fda6a1ab150a43 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 3 May 2017 10:56:29 +0100 Subject: [PATCH 17/20] ARM: dts: rockchip: enable ARM Mali GPU on rk3288-veyron Add reference to the Mali GPU device tree node on rk3288-veyron. Tested on Minnie and Jerry boards. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Guillaume Tucker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 5d1eb0a25827..d709fa1847f9 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -161,6 +161,11 @@ &emmc { pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; From 23c0c210a1adcfca27a52808d1a0cbd807e86518 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Tue, 30 May 2017 23:52:46 +0800 Subject: [PATCH 18/20] ARM: dts: rockchip: add adc button for Firefly The only adc button connected to adc input is recovery button. Signed-off-by: Randy Li Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly-reload.dts | 17 +++++++++++++++++ arch/arm/boot/dts/rk3288-firefly.dtsi | 13 +++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index d0b3204a4799..b11a282c334c 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -48,6 +48,19 @@ / { model = "Firefly-RK3288-reload"; compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -246,6 +259,10 @@ &i2s { status = "okay"; }; +&saradc { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 864747342e3e..32dabae12e67 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -49,6 +49,19 @@ memory@0 { reg = <0 0x80000000>; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + dovdd_1v8: dovdd-1v8-regulator { compatible = "regulator-fixed"; regulator-name = "dovdd_1v8"; From 3880af4541a178b38cce0456c9afa3ab96534e90 Mon Sep 17 00:00:00 2001 From: William Wu Date: Fri, 2 Jun 2017 15:04:24 +0800 Subject: [PATCH 19/20] ARM: dts: rockchip: add usb nodes on rk322x This patch adds usb otg/host controllers and phys nodes on rk322x. Signed-off-by: William Wu Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 138 +++++++++++++++++++++++++++++++++- 1 file changed, 137 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index df574135797a..f3e4ffd9f818 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -210,8 +210,61 @@ i2s2: i2s2@100e0000 { }; grf: syscon@11000000 { - compatible = "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x11000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@760 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0760 0x0c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + u2phy1: usb2-phy@800 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0800 0x0c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_otg: otg-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; uart0: serial@11010000 { @@ -467,6 +520,89 @@ emmc: dwmmc@30020000 { status = "disabled"; }; + usb_otg: usb@30040000 { + compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x30040000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + g-use-dma; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ehci: usb@30080000 { + compatible = "generic-ehci"; + reg = <0x30080000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@300a0000 { + compatible = "generic-ohci"; + reg = <0x300a0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@300c0000 { + compatible = "generic-ehci"; + reg = <0x300c0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@300e0000 { + compatible = "generic-ohci"; + reg = <0x300e0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host2_ehci: usb@30100000 { + compatible = "generic-ehci"; + reg = <0x30100000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; + clock-names = "usbhost", "utmi"; + status = "disabled"; + }; + + usb_host2_ohci: usb@30120000 { + compatible = "generic-ohci"; + reg = <0x30120000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + gmac: ethernet@30200000 { compatible = "rockchip,rk3228-gmac"; reg = <0x30200000 0x10000>; From 81b61d37705173b8b9eb52c4566a8fc7c7099520 Mon Sep 17 00:00:00 2001 From: William Wu Date: Fri, 2 Jun 2017 15:04:25 +0800 Subject: [PATCH 20/20] ARM: dts: rockchip: enable usb for rk3229 evb board Rockchip's rk3229 evaluation board has one usb otg controller and three usb host controllers. Each usb controller connect with one usb2 phy port through UTMI+ interface. And the three usb host interfaces use the same GPIO VBUS drive. Let's enable them to support usb on rk3229 evb board. Signed-off-by: William Wu Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3229-evb.dts | 74 ++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 275092a950ef..1b55192b7d04 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -58,6 +58,17 @@ ext_gmac: ext_gmac { #clock-cells = <0>; }; + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + }; + vcc_phy: vcc-phy-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -85,6 +96,69 @@ &gmac { status = "okay"; }; +&pinctrl { + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + &uart2 { status = "okay"; }; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_ehci { + status = "okay"; +}; + +&usb_host2_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +};