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arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support
Add initial device tree support for Axis ARTPEC-8 SoC. This SoC contains 4 Cortex-A53 CPUs and several other peripheral IPs. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250901051926.59970-5-ravi.patel@samsung.com Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
SungMin Park
Krzysztof Kozlowski
parent
604a932fa9
commit
639f8e36ba
12
MAINTAINERS
12
MAINTAINERS
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@ -4102,6 +4102,18 @@ S: Maintained
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F: Documentation/devicetree/bindings/sound/axentia,*
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F: sound/soc/atmel/tse850-pcm5142.c
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AXIS ARTPEC ARM64 SoC SUPPORT
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M: Jesper Nilsson <jesper.nilsson@axis.com>
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M: Lars Persson <lars.persson@axis.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-samsung-soc@vger.kernel.org
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L: linux-arm-kernel@axis.com
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S: Maintained
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F: Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml
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F: arch/arm64/boot/dts/exynos/axis/
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F: drivers/clk/samsung/clk-artpec*.c
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F: include/dt-bindings/clock/axis,artpec*-clk.h
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AXI-FAN-CONTROL HARDWARE MONITOR DRIVER
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M: Nuno Sá <nuno.sa@analog.com>
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L: linux-hwmon@vger.kernel.org
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@ -40,6 +40,13 @@ config ARCH_APPLE
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This enables support for Apple's in-house ARM SoC family, such
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as the Apple M1.
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config ARCH_ARTPEC
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bool "Axis Communications ARTPEC SoC Family"
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depends on ARCH_EXYNOS
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select ARM_GIC
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help
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This enables support for the ARMv8 based ARTPEC SoC Family.
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config ARCH_AXIADO
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bool "Axiado SoC Family"
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select GPIOLIB
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@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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subdir-y += axis
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subdir-y += google
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dtb-$(CONFIG_ARCH_EXYNOS) += \
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36
arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
Normal file
36
arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
Normal file
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@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Axis ARTPEC-8 SoC device tree pinctrl constants
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*
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* Copyright (c) 2025 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2025 Axis Communications AB.
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* https://www.axis.com
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*/
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#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
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#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
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#define ARTPEC_PIN_PULL_NONE 0
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#define ARTPEC_PIN_PULL_DOWN 1
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#define ARTPEC_PIN_PULL_UP 3
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#define ARTPEC_PIN_FUNC_INPUT 0
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#define ARTPEC_PIN_FUNC_OUTPUT 1
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#define ARTPEC_PIN_FUNC_2 2
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#define ARTPEC_PIN_FUNC_3 3
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#define ARTPEC_PIN_FUNC_4 4
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#define ARTPEC_PIN_FUNC_5 5
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#define ARTPEC_PIN_FUNC_6 6
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#define ARTPEC_PIN_FUNC_EINT 0xf
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#define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT
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/* Drive strength for ARTPEC */
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#define ARTPEC_PIN_DRV_SR1 0x8
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#define ARTPEC_PIN_DRV_SR2 0x9
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#define ARTPEC_PIN_DRV_SR3 0xa
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#define ARTPEC_PIN_DRV_SR4 0xb
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#define ARTPEC_PIN_DRV_SR5 0xc
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#define ARTPEC_PIN_DRV_SR6 0xd
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#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */
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120
arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
Normal file
120
arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
Normal file
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@ -0,0 +1,120 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Axis ARTPEC-8 SoC pin-mux and pin-config device tree source
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*
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* Copyright (c) 2025 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2025 Axis Communications AB.
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* https://www.axis.com
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*/
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#include "artpec-pinctrl.h"
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&pinctrl_fsys {
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gpe0: gpe0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe1: gpe1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe2: gpe2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf0: gpf0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf1: gpf1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf2: gpf2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf3: gpf3-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf4: gpf4-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gps0: gps0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gps1: gps1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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serial0_bus: serial0-bus-pins {
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samsung,pins = "gpf4-4", "gpf4-5";
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samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
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samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
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samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
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};
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};
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&pinctrl_peric {
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gpa0: gpa0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpa1: gpa1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpa2: gpa2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpk0: gpk0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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244
arch/arm64/boot/dts/exynos/axis/artpec8.dtsi
Normal file
244
arch/arm64/boot/dts/exynos/axis/artpec8.dtsi
Normal file
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@ -0,0 +1,244 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Axis ARTPEC-8 SoC device tree source
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*
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* Copyright (c) 2025 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2025 Axis Communications AB.
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* https://www.axis.com
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/axis,artpec8-clk.h>
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/ {
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compatible = "axis,artpec8";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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pinctrl0 = &pinctrl_fsys;
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pinctrl1 = &pinctrl_peric;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>;
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clock-names = "cpu";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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};
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idle-states {
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entry-method = "psci";
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cpu_sleep: cpu-sleep {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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local-timer-stop;
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entry-latency-us = <300>;
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exit-latency-us = <1200>;
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min-residency-us = <2000>;
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};
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};
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};
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fin_pll: clock-finpll {
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compatible = "fixed-factor-clock";
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clocks = <&osc_clk>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "fin_pll";
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};
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osc_clk: clock-osc {
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/* XXTI */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "osc_clk";
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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soc: soc@0 {
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compatible = "simple-bus";
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ranges = <0x0 0x0 0x0 0x17000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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cmu_imem: clock-controller@10010000 {
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compatible = "axis,artpec8-cmu-imem";
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reg = <0x10010000 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>,
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<&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>;
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clock-names = "fin_pll", "aclk", "jpeg";
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};
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timer@10040000 {
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compatible = "axis,artpec8-mct", "samsung,exynos4210-mct";
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reg = <0x10040000 0x1000>;
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clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>;
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clock-names = "fin_pll", "mct";
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interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@10201000 {
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compatible = "arm,gic-400";
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reg = <0x10201000 0x1000>,
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<0x10202000 0x2000>,
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<0x10204000 0x2000>,
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<0x10206000 0x2000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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cmu_cpucl: clock-controller@11410000 {
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compatible = "axis,artpec8-cmu-cpucl";
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reg = <0x11410000 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>;
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clock-names = "fin_pll", "switch";
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};
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cmu_cmu: clock-controller@12400000 {
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compatible = "axis,artpec8-cmu-cmu";
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reg = <0x12400000 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>;
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clock-names = "fin_pll";
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};
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cmu_core: clock-controller@12410000 {
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compatible = "axis,artpec8-cmu-core";
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reg = <0x12410000 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>,
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<&cmu_cmu CLK_DOUT_CMU_CORE_DLP>;
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clock-names = "fin_pll", "main", "dlp";
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};
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cmu_bus: clock-controller@12c10000 {
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compatible = "axis,artpec8-cmu-bus";
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reg = <0x12c10000 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_BUS>,
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<&cmu_cmu CLK_DOUT_CMU_BUS_DLP>;
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clock-names = "fin_pll", "bus", "dlp";
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};
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cmu_peri: clock-controller@16410000 {
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compatible = "axis,artpec8-cmu-peri";
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reg = <0x16410000 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_PERI_IP>,
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<&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>,
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<&cmu_cmu CLK_DOUT_CMU_PERI_DISP>;
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clock-names = "fin_pll", "ip", "audio", "disp";
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};
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pinctrl_peric: pinctrl@165f0000 {
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compatible = "axis,artpec8-pinctrl";
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reg = <0x165f0000 0x1000>;
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interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmu_fsys: clock-controller@16c10000 {
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compatible = "axis,artpec8-cmu-fsys";
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reg = <0x16c10000 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
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clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
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};
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pinctrl_fsys: pinctrl@16c30000 {
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compatible = "axis,artpec8-pinctrl";
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reg = <0x16c30000 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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};
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serial_0: serial@16cc0000 {
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compatible = "axis,artpec8-uart";
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reg = <0x16cc0000 0x100>;
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clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>,
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<&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>;
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clock-names = "uart", "clk_uart_baud0";
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||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&serial0_bus>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user