From 5e494e2a9d8c7406e49c39f42bd71ae644c1a1f7 Mon Sep 17 00:00:00 2001 From: Huang Yiwei Date: Fri, 29 Jul 2022 22:34:22 +0800 Subject: [PATCH] phy: qcom: Add UFS PHY driver snapshot for Kalama Add UFS PHY driver snapshot from msm-5.15 branch with base commit (Merge "Revert "arm64: defconfig: Enable QCOM_DYN_MINIDUMP_STACK for kalama""). Change-Id: I622debd9c08a5936469c4220f933e33e8a19ce81 Signed-off-by: Huang Yiwei --- drivers/phy/qualcomm/Kconfig | 6 + drivers/phy/qualcomm/Makefile | 1 + .../phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.c | 325 ++++++++++++++++++ .../phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.h | 269 +++++++++++++++ 4 files changed, 601 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.c create mode 100644 drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.h diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 9e09925e200d..81c14056b29e 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -71,6 +71,12 @@ config PHY_QCOM_UFS if PHY_QCOM_UFS +config PHY_QCOM_UFS_V4 + tristate + default PHY_QCOM_UFS + help + Support for 7nm UFS QMP phy present on QCOM chipsets. + config PHY_QCOM_UFS_QRBTC_SDM845 tristate "Qualcomm Technologies, Inc. UFS Presil Phy Driver" depends on PHY_QCOM_UFS && REGULATOR_STUB diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index bae4d9e981fa..04591a8416b9 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o +obj-$(CONFIG_PHY_QCOM_UFS_V4) += phy-qcom-ufs-qmp-v4-kalama.o obj-$(CONFIG_PHY_QCOM_UFS_QRBTC_SDM845) += phy-qcom-ufs-qrbtc-sdm845.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.c b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.c new file mode 100644 index 000000000000..cbd76f8454aa --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Linux Foundation. All rights reserved. + */ + +#include "phy-qcom-ufs-qmp-v4-kalama.h" + +#define UFS_PHY_NAME "ufs_phy_qmp_v4_kalama" + +static inline void ufs_qcom_phy_qmp_v4_start_serdes(struct ufs_qcom_phy *phy); +static int ufs_qcom_phy_qmp_v4_is_pcs_ready(struct ufs_qcom_phy *phy_common); + +static int ufs_qcom_phy_qmp_v4_phy_calibrate(struct phy *generic_phy) +{ + struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); + struct device *dev = ufs_qcom_phy->dev; + bool is_rate_B; + int submode; + int err; + + err = reset_control_assert(ufs_qcom_phy->ufs_reset); + if (err) { + dev_err(dev, "Failed to assert UFS PHY reset %d\n", err); + goto out; + } + + /* For UFS PHY's submode, 2 = G5, 1 = G4, 0 = non-G4/G5 */ + submode = ufs_qcom_phy->submode; + is_rate_B = (ufs_qcom_phy->mode == PHY_MODE_UFS_HS_B) ? true : false; + + writel_relaxed(0x01, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET); + /* Ensure PHY is in reset before writing PHY calibration data */ + wmb(); + /* + * Writing PHY calibration in this order: + * 1. Write Rate-A calibration first (1-lane mode). + * 2. Write 2nd lane configuration if needed. + * 3. Write Rate-B calibration overrides + */ + if (submode == UFS_QCOM_PHY_SUBMODE_G5) { + ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_g5, + ARRAY_SIZE(phy_cal_table_rate_A_g5)); + if (ufs_qcom_phy->lanes_per_direction == 2) + ufs_qcom_phy_write_tbl(ufs_qcom_phy, + phy_cal_table_2nd_lane, + ARRAY_SIZE(phy_cal_table_2nd_lane)); + } else if (submode == UFS_QCOM_PHY_SUBMODE_G4) { + ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_g4, + ARRAY_SIZE(phy_cal_table_rate_A_g4)); + if (ufs_qcom_phy->lanes_per_direction == 2) + ufs_qcom_phy_write_tbl(ufs_qcom_phy, + phy_cal_table_2nd_lane, + ARRAY_SIZE(phy_cal_table_2nd_lane)); + } else { + dev_err(dev, "%s: unsupported submode.\n"); + return -EOPNOTSUPP; + } + + if (is_rate_B && submode == UFS_QCOM_PHY_SUBMODE_G4) + ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B, + ARRAY_SIZE(phy_cal_table_rate_B)); + + writel_relaxed(0x00, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET); + /* flush buffered writes */ + wmb(); + + err = reset_control_deassert(ufs_qcom_phy->ufs_reset); + if (err) { + dev_err(dev, "Failed to deassert UFS PHY reset %d\n", err); + goto out; + } + + ufs_qcom_phy_qmp_v4_start_serdes(ufs_qcom_phy); + + err = ufs_qcom_phy_qmp_v4_is_pcs_ready(ufs_qcom_phy); + +out: + return err; +} + +static int ufs_qcom_phy_qmp_v4_init(struct phy *generic_phy) +{ + struct ufs_qcom_phy_qmp_v4 *phy = phy_get_drvdata(generic_phy); + struct ufs_qcom_phy *phy_common = &phy->common_cfg; + int err; + + err = ufs_qcom_phy_init_clks(phy_common); + if (err) { + dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n", + __func__, err); + goto out; + } + + err = ufs_qcom_phy_init_vregulators(phy_common); + if (err) { + dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n", + __func__, err); + goto out; + } + + /* Optional */ + ufs_qcom_phy_get_reset(phy_common); + +out: + return err; +} + +static int ufs_qcom_phy_qmp_v4_exit(struct phy *generic_phy) +{ + return 0; +} + +static +int ufs_qcom_phy_qmp_v4_set_mode(struct phy *generic_phy, + enum phy_mode mode, int submode) +{ + struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy); + + phy_common->mode = PHY_MODE_INVALID; + + if (mode > 0) + phy_common->mode = mode; + + phy_common->submode = submode; + + return 0; +} + +static inline +void ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(struct ufs_qcom_phy *phy, + bool enable) +{ + u32 temp; + + temp = readl_relaxed(phy->mmio + QSERDES_RX0_RX_INTERFACE_MODE); + if (enable) + temp |= QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT; + else + temp &= ~QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT; + writel_relaxed(temp, phy->mmio + QSERDES_RX0_RX_INTERFACE_MODE); + + if (phy->lanes_per_direction == 1) + goto out; + + temp = readl_relaxed(phy->mmio + QSERDES_RX1_RX_INTERFACE_MODE); + if (enable) + temp |= QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT; + else + temp &= ~QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT; + writel_relaxed(temp, phy->mmio + QSERDES_RX1_RX_INTERFACE_MODE); + +out: + /* ensure register value is committed */ + mb(); +} + +static +void ufs_qcom_phy_qmp_v4_power_control(struct ufs_qcom_phy *phy, + bool power_ctrl) +{ + if (!power_ctrl) { + /* apply analog power collapse */ + writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); + /* + * Make sure that PHY knows its analog rail is going to be + * powered OFF. + */ + mb(); + ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(phy, true); + } else { + ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(phy, false); + /* bring PHY out of analog power collapse */ + writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); + + /* + * Before any transactions involving PHY, ensure PHY knows + * that it's analog rail is powered ON. + */ + mb(); + } +} + +static inline +void ufs_qcom_phy_qmp_v4_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val) +{ + /* + * v4 PHY does not have TX_LANE_ENABLE register. + * Implement this function so as not to propagate error to caller. + */ +} + +static +void ufs_qcom_phy_qmp_v4_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl) +{ + u32 temp; + + temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE); + + if (ctrl) /* enable RX LineCfg */ + temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT; + else /* disable RX LineCfg */ + temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT; + + writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE); + /* make sure that RX LineCfg config applied before we return */ + mb(); +} + +static inline void ufs_qcom_phy_qmp_v4_start_serdes(struct ufs_qcom_phy *phy) +{ + u32 tmp; + + tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START); + tmp &= ~MASK_SERDES_START; + tmp |= (1 << OFFSET_SERDES_START); + writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START); + /* Ensure register value is committed */ + mb(); +} + +static int ufs_qcom_phy_qmp_v4_is_pcs_ready(struct ufs_qcom_phy *phy_common) +{ + int err = 0; + u32 val; + + err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS, + val, (val & MASK_PCS_READY), 10, 1000000); + if (err) { + dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n", + __func__, err); + goto out; + } + +out: + return err; +} + + +static void ufs_qcom_phy_qmp_v4_dbg_register_dump(struct ufs_qcom_phy *phy) +{ + ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE, + "PHY QSERDES COM Registers "); + ufs_qcom_phy_dump_regs(phy, PCS2_BASE, PCS2_SIZE, + "PHY PCS2 Registers "); + ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE, + "PHY Registers "); + ufs_qcom_phy_dump_regs(phy, RX_BASE(0), RX_SIZE, + "PHY RX0 Registers "); + ufs_qcom_phy_dump_regs(phy, TX_BASE(0), TX_SIZE, + "PHY TX0 Registers "); + ufs_qcom_phy_dump_regs(phy, RX_BASE(1), RX_SIZE, + "PHY RX1 Registers "); + ufs_qcom_phy_dump_regs(phy, TX_BASE(1), TX_SIZE, + "PHY TX1 Registers "); +} + +static const struct phy_ops ufs_qcom_phy_qmp_v4_phy_ops = { + .init = ufs_qcom_phy_qmp_v4_init, + .exit = ufs_qcom_phy_qmp_v4_exit, + .power_on = ufs_qcom_phy_power_on, + .power_off = ufs_qcom_phy_power_off, + .set_mode = ufs_qcom_phy_qmp_v4_set_mode, + .calibrate = ufs_qcom_phy_qmp_v4_phy_calibrate, + .owner = THIS_MODULE, +}; + +static struct ufs_qcom_phy_specific_ops phy_v4_ops = { + .start_serdes = ufs_qcom_phy_qmp_v4_start_serdes, + .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_v4_is_pcs_ready, + .set_tx_lane_enable = ufs_qcom_phy_qmp_v4_set_tx_lane_enable, + .ctrl_rx_linecfg = ufs_qcom_phy_qmp_v4_ctrl_rx_linecfg, + .power_control = ufs_qcom_phy_qmp_v4_power_control, + .dbg_register_dump = ufs_qcom_phy_qmp_v4_dbg_register_dump, +}; + +static int ufs_qcom_phy_qmp_v4_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy *generic_phy; + struct ufs_qcom_phy_qmp_v4 *phy; + int err = 0; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) { + err = -ENOMEM; + goto out; + } + + generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg, + &ufs_qcom_phy_qmp_v4_phy_ops, &phy_v4_ops); + + if (!generic_phy) { + dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n", + __func__); + err = -EIO; + goto out; + } + + phy_set_drvdata(generic_phy, phy); + + strscpy(phy->common_cfg.name, UFS_PHY_NAME, + sizeof(phy->common_cfg.name)); + +out: + return err; +} + +static const struct of_device_id ufs_qcom_phy_qmp_v4_of_match[] = { + {.compatible = "qcom,ufs-phy-qmp-v4-kalama"}, + {}, +}; +MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v4_of_match); + +static struct platform_driver ufs_qcom_phy_qmp_v4_driver = { + .probe = ufs_qcom_phy_qmp_v4_probe, + .driver = { + .of_match_table = ufs_qcom_phy_qmp_v4_of_match, + .name = "ufs_qcom_phy_qmp_v4_kalama", + }, +}; + +module_platform_driver(ufs_qcom_phy_qmp_v4_driver); + +MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v4 KALAMA"); +MODULE_LICENSE("GPL"); diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.h b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.h new file mode 100644 index 000000000000..8a725be348ea --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-kalama.h @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef UFS_QCOM_PHY_QMP_V4_H_ +#define UFS_QCOM_PHY_QMP_V4_H_ + +#include "phy-qcom-ufs-i.h" + +/* QCOM UFS PHY control registers */ +#define COM_BASE 0x000 +#define COM_SIZE 0x200 +#define PHY_BASE 0x400 +#define PHY_SIZE 0x258 +#define PCS2_BASE 0x800 +#define PCS2_SIZE 0x64 +#define TX_BASE(n) (0x1000 + (0x800 * n)) +#define TX_SIZE 0x134 +#define RX_BASE(n) (0x1200 + (0x800 * n)) +#define RX_SIZE 0x3D8 +#define COM_OFF(x) (COM_BASE + x) +#define PHY_OFF(x) (PHY_BASE + x) +#define TX_OFF(n, x) (TX_BASE(n) + x) +#define RX_OFF(n, x) (RX_BASE(n) + x) + +#define UFS_PHY_SW_RESET PHY_OFF(0x8) +#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x4) +#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x30) +#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x18C) + +#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x110) +#define QSERDES_COM_CMN_CONFIG_1 COM_OFF(0x174) +#define QSERDES_COM_HSCLK_SEL_1 COM_OFF(0x3C) +#define QSERDES_COM_HSCLK_HS_SWITCH_SEL_1 COM_OFF(0x9C) +#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0x120) +#define QSERDES_COM_PLL_IVCO COM_OFF(0xF4) +#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x148) +#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0x88) +#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x70) +#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x74) +#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x78) +#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0x80) +#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0x84) + +#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0x28) +#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x10) +#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x14) +#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x18) +#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0x20) +#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0x24) + +#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x140) + +#define QSERDES_TX0_TX_FR_DCC_CTRL TX_OFF(0, 0x108) +#define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x7C) +#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX TX_OFF(0, 0x30) + +#define QSERDES_RX0_RX_MODE_RATE_0_1_B0 RX_OFF(0, 0x208) +#define QSERDES_RX0_RX_MODE_RATE_0_1_B1 RX_OFF(0, 0x20C) +#define QSERDES_RX0_RX_MODE_RATE_0_1_B3 RX_OFF(0, 0x214) +#define QSERDES_RX0_RX_MODE_RATE_0_1_B6 RX_OFF(0, 0x220) +#define QSERDES_RX0_RX_MODE_RATE2_B3 RX_OFF(0, 0x238) +#define QSERDES_RX0_RX_MODE_RATE2_B6 RX_OFF(0, 0x244) +#define QSERDES_RX0_RX_MODE_RATE3_B3 RX_OFF(0, 0x25C) +#define QSERDES_RX0_RX_MODE_RATE3_B4 RX_OFF(0, 0x260) +#define QSERDES_RX0_RX_MODE_RATE3_B5 RX_OFF(0, 0x264) +#define QSERDES_RX0_RX_MODE_RATE3_B8 RX_OFF(0, 0x270) +#define QSERDES_RX0_RX_MODE_RATE4_B3 RX_OFF(0, 0x280) +#define QSERDES_RX0_RX_MODE_RATE4_B6 RX_OFF(0, 0x28C) +#define QSERDES_RX0_RX_INTERFACE_MODE RX_OFF(0, 0x1E0) +#define QSERDES_RX0_UCDR_FO_GAIN_RATE2 RX_OFF(0, 0xD4) +#define QSERDES_RX0_UCDR_FO_GAIN_RATE4 RX_OFF(0, 0xDC) +#define QSERDES_RX0_VGA_CAL_MAN_VAL RX_OFF(0, 0x178) + +#define QSERDES_RX1_RX_MODE_RATE_0_1_B0 RX_OFF(1, 0x208) +#define QSERDES_RX1_RX_MODE_RATE_0_1_B1 RX_OFF(1, 0x20C) +#define QSERDES_RX1_RX_MODE_RATE_0_1_B3 RX_OFF(1, 0x214) +#define QSERDES_RX1_RX_MODE_RATE_0_1_B6 RX_OFF(1, 0x220) +#define QSERDES_RX1_RX_MODE_RATE2_B3 RX_OFF(1, 0x238) +#define QSERDES_RX1_RX_MODE_RATE2_B6 RX_OFF(1, 0x244) +#define QSERDES_RX1_RX_MODE_RATE3_B3 RX_OFF(1, 0x25C) +#define QSERDES_RX1_RX_MODE_RATE3_B4 RX_OFF(1, 0x260) +#define QSERDES_RX1_RX_MODE_RATE3_B5 RX_OFF(1, 0x264) +#define QSERDES_RX1_RX_MODE_RATE3_B8 RX_OFF(1, 0x270) +#define QSERDES_RX1_RX_MODE_RATE4_B3 RX_OFF(1, 0x280) +#define QSERDES_RX1_RX_MODE_RATE4_B6 RX_OFF(1, 0x28C) +#define QSERDES_RX1_RX_INTERFACE_MODE RX_OFF(1, 0x1E0) +#define QSERDES_RX1_UCDR_FO_GAIN_RATE2 RX_OFF(1, 0xD4) +#define QSERDES_RX1_UCDR_FO_GAIN_RATE4 RX_OFF(1, 0xDC) +#define QSERDES_RX1_VGA_CAL_MAN_VAL RX_OFF(1, 0x178) + +#define QSERDES_TX1_LANE_MODE_1 TX_OFF(1, 0x7C) +#define QSERDES_TX1_TX_FR_DCC_CTRL TX_OFF(1, 0x108) +#define QSERDES_TX1_RES_CODE_LANE_OFFSET_TX TX_OFF(1, 0x30) + +#define UFS_PHY_MULTI_LANE_CTRL1 PHY_OFF(0x1FC) +#define UFS_PHY_TX_MID_TERM_CTRL1 PHY_OFF(0x1F4) +#define UFS_PHY_PLL_CNTL PHY_OFF(0x2C) + +#define UFS_PHY_TX_HSGEAR_CAPABILITY PHY_OFF(0x74) +#define UFS_PHY_RX_HSGEAR_CAPABILITY PHY_OFF(0xBC) + +#define UFS_PHY_PHY_START PHY_OFF(0x0) +#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x1A8) +#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x17C) + +#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) +#define QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT BIT(6) + +/* + * This structure represents the v4 specific phy. + * common_cfg MUST remain the first field in this structure + * in case extra fields are added. This way, when calling + * get_ufs_qcom_phy() of generic phy, we can extract the + * common phy structure (struct ufs_qcom_phy) out of it + * regardless of the relevant specific phy. + */ +struct ufs_qcom_phy_qmp_v4 { + struct ufs_qcom_phy common_cfg; +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g5[] = { + + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x1), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD9), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG_1, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL_1, 0x11), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x41), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0A), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x18), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x14), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0x7F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x06), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x05), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x07), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN_RATE2, 0x0C), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN_RATE4, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_VGA_CAL_MAN_VAL, 0x0E), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B0, 0xC2), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B1, 0xC2), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B3, 0x1A), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B6, 0x60), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE2_B3, 0x9E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE2_B6, 0x60), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B3, 0x9E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B4, 0x0E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B5, 0x36), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B8, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B3, 0xB9), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B6, 0xFF), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x05), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x07), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN_RATE2, 0x0C), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN_RATE4, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_VGA_CAL_MAN_VAL, 0x0E), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B0, 0xC2), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B1, 0xC2), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B3, 0x1A), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B6, 0x60), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE2_B3, 0x9E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE2_B6, 0x60), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B3, 0x9E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B4, 0x0E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B5, 0x36), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B8, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B3, 0xB9), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B6, 0xFF), + + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x00), + + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x33), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x69), +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g4[] = { + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x1), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD9), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG_1, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL_1, 0x11), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x41), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0A), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x18), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x14), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0x7F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x06), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x4C), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0A), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x18), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x14), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x99), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x07), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x05), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_TX_FR_DCC_CTRL, 0x4C), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x07), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN_RATE2, 0x0C), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_VGA_CAL_MAN_VAL, 0x0E), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B0, 0xC2), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B1, 0xC2), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B3, 0x1A), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B6, 0x60), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE2_B3, 0x9E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE2_B6, 0x60), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B3, 0x9E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B4, 0x0E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B5, 0x36), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B8, 0x02), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x05), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_TX_FR_DCC_CTRL, 0x4C), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x07), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN_RATE2, 0x0C), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_VGA_CAL_MAN_VAL, 0x0E), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B0, 0xC2), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B1, 0xC2), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B3, 0x1A), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B6, 0x60), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE2_B3, 0x9E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE2_B6, 0x60), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B3, 0x9E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B4, 0x0E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B5, 0x36), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B8, 0x02), + + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x00), + + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x2B), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x69), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x04), +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02), +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44), +}; + +#endif