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drm/msm/a6xx: Add support for A650 speed binning
Add support for matching QFPROM fuse values to get the correct speed bin on A650 (SM8250) GPUs. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530043/ Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-2-2dede22dd7f7@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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@ -1847,6 +1847,21 @@ static u32 a640_get_speed_bin(u32 fuse)
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return UINT_MAX;
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}
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static u32 a650_get_speed_bin(u32 fuse)
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{
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if (fuse == 0)
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return 0;
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else if (fuse == 1)
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return 1;
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/* Yep, 2 and 3 are swapped! :/ */
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else if (fuse == 2)
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return 3;
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else if (fuse == 3)
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return 2;
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return UINT_MAX;
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}
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static u32 adreno_7c3_get_speed_bin(u32 fuse)
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{
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if (fuse == 0)
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@ -1875,6 +1890,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
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if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
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val = a640_get_speed_bin(fuse);
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if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
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val = a650_get_speed_bin(fuse);
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if (val == UINT_MAX) {
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DRM_DEV_ERROR(dev,
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"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
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