mirror of
https://github.com/torvalds/linux.git
synced 2026-06-05 04:56:13 +02:00
Merge tag 'drm-misc-next-2023-03-31' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v6.4-rc1: Cross-subsystem Changes: - DT bindings update for adding Mali MT81xx devices. - Assorted DT binding updates. Core Changes: - Documentation update to scheduler. Driver Changes: - Add support for the same mali devices. - Add support for speed binning to panfrost. - Add B133UAN01.0 eDP panel. - Assorted small fixes to bridge/ps8640, bridge/it6505, panel/magnachip. - Use of_property_read_bool in ps8622 and ofdrm. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/36f4efa4-26e9-49df-287e-d193422c990d@linux.intel.com
This commit is contained in:
Daniel Vetter
commit
63758fec65
|
|
@ -10,7 +10,7 @@ maintainers:
|
|||
- Robin van der Gracht <robin@protonic.nl>
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/input/matrix-keymap.yaml#"
|
||||
- $ref: /schemas/input/matrix-keymap.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
# Copyright 2019 BayLibre, SAS
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
# Copyright 2019 BayLibre, SAS
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic Meson Display Controller
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
# Copyright 2019 Analogix Semiconductor, Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analogix ANX7625 SlimPort (4K Mobile HD Transmitter)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cadence MHDP8546 bridge
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
edid-emulation:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
The EDID emulation entry to use
|
||||
Value Resolution Description
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ properties:
|
|||
i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
|
||||
|
||||
clock-names:
|
||||
const: "ref"
|
||||
const: ref
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ description:
|
|||
|
||||
properties:
|
||||
$nodename:
|
||||
const: "aux-bus"
|
||||
const: aux-bus
|
||||
|
||||
panel:
|
||||
$ref: panel/panel-common.yaml#
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
# Copyright 2019 NXP
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: iMX8MQ Display Controller Subsystem (DCSS)
|
||||
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ properties:
|
|||
- const: hdmi
|
||||
|
||||
mediatek,syscon-hdmi:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to system configuration registers
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ properties:
|
|||
|
||||
syscon-sfpb:
|
||||
description: A phandle to mmss_sfpb syscon node (only for DSIv2).
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
qcom,dual-dsi-mode:
|
||||
type: boolean
|
||||
|
|
@ -105,14 +105,14 @@ properties:
|
|||
type: object
|
||||
|
||||
ports:
|
||||
$ref: "/schemas/graph.yaml#/properties/ports"
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains DSI controller input and output ports as children, each
|
||||
containing one endpoint subnode.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: "/schemas/graph.yaml#/$defs/port-base"
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: |
|
||||
Input endpoints of the controller.
|
||||
|
|
@ -128,7 +128,7 @@ properties:
|
|||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
port@1:
|
||||
$ref: "/schemas/graph.yaml#/$defs/port-base"
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: |
|
||||
Output endpoints of the controller.
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ properties:
|
|||
maximum: 31
|
||||
|
||||
qcom,phy-drive-ldo-level:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
The PHY LDO has an amplitude tuning feature to adjust the LDO output
|
||||
for the HSTX drive. Use supported levels (mV) to offset the drive level
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
%YAML 1.2
|
||||
---
|
||||
|
||||
$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: GMU attached to certain Adreno GPUs
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
%YAML 1.2
|
||||
---
|
||||
|
||||
$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/msm/gpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Adreno or Snapdragon GPUs
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/msm/mdp4.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Adreno/Snapdragon MDP4 display controller
|
||||
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@ properties:
|
|||
description: phandle of the backlight device attached to the panel
|
||||
|
||||
port: true
|
||||
rotation: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
|
|
@ -1,43 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/innolux,p120zdg-bf1.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel
|
||||
|
||||
maintainers:
|
||||
- Sandeep Panda <spanda@codeaurora.org>
|
||||
- Douglas Anderson <dianders@chromium.org>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: innolux,p120zdg-bf1
|
||||
|
||||
enable-gpios: true
|
||||
power-supply: true
|
||||
backlight: true
|
||||
no-hpd: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- power-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
panel_edp: panel-edp {
|
||||
compatible = "innolux,p120zdg-bf1";
|
||||
enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>;
|
||||
power-supply = <&pm8916_l2>;
|
||||
backlight = <&backlight>;
|
||||
no-hpd;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -34,7 +34,7 @@ properties:
|
|||
description: phandle of gpio for reset line - This should be 8mA, gpio
|
||||
can be configured using mux, pinctrl, pinctrl-names (active high)
|
||||
|
||||
vddi0-supply:
|
||||
vddio-supply:
|
||||
description: phandle of the regulator that provides the supply voltage
|
||||
Power IC supply
|
||||
|
||||
|
|
@ -51,7 +51,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vddi0-supply
|
||||
- vddio-supply
|
||||
- vddpos-supply
|
||||
- vddneg-supply
|
||||
- reset-gpios
|
||||
|
|
@ -70,7 +70,7 @@ examples:
|
|||
panel@0 {
|
||||
compatible = "tianma,fhd-video", "novatek,nt36672a";
|
||||
reg = <0>;
|
||||
vddi0-supply = <&vreg_l14a_1p88>;
|
||||
vddio-supply = <&vreg_l14a_1p88>;
|
||||
vddpos-supply = <&lab>;
|
||||
vddneg-supply = <&ibb>;
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ description: |
|
|||
|
||||
If the panel is more advanced a dedicated binding file is required.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
|
||||
compatible:
|
||||
|
|
@ -67,12 +64,31 @@ properties:
|
|||
reset-gpios: true
|
||||
port: true
|
||||
power-supply: true
|
||||
vddio-supply: true
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s6e3fc2x01
|
||||
- samsung,sofef00
|
||||
then:
|
||||
properties:
|
||||
power-supply: false
|
||||
required:
|
||||
- vddio-supply
|
||||
else:
|
||||
properties:
|
||||
vddio-supply: false
|
||||
required:
|
||||
- power-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- power-supply
|
||||
- reg
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -192,6 +192,8 @@ properties:
|
|||
- innolux,n125hce-gn1
|
||||
# InnoLux 15.6" WXGA TFT LCD panel
|
||||
- innolux,n156bge-l21
|
||||
# Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel
|
||||
- innolux,p120zdg-bf1
|
||||
# Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
|
||||
- innolux,zj070na-01p
|
||||
# King & Display KD116N21-30NV-A010 eDP TFT LCD panel
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ properties:
|
|||
|
||||
backlight:
|
||||
description: Backlight used by the panel
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ properties:
|
|||
compatible:
|
||||
const: samsung,s6e88a0-ams452ef01
|
||||
reg: true
|
||||
port: true
|
||||
reset-gpios: true
|
||||
vdd3-supply:
|
||||
description: core voltage supply
|
||||
|
|
@ -25,6 +26,7 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- port
|
||||
- vdd3-supply
|
||||
- vci-supply
|
||||
- reset-gpios
|
||||
|
|
@ -46,5 +48,11 @@ examples:
|
|||
vdd3-supply = <&pm8916_l17>;
|
||||
vci-supply = <®_vlcd_vci>;
|
||||
reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel
|
||||
|
||||
maintainers:
|
||||
- Marco Franchi <marco.franchi@nxp.com>
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
|
|
|||
|
|
@ -19,6 +19,8 @@ properties:
|
|||
compatible:
|
||||
const: visionox,rm69299-1080p-display
|
||||
|
||||
reg: true
|
||||
|
||||
vdda-supply:
|
||||
description: |
|
||||
Phandle of the regulator that provides the vdda supply voltage.
|
||||
|
|
@ -34,6 +36,7 @@ additionalProperties: false
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vdda-supply
|
||||
- vdd3p3-supply
|
||||
- reset-gpios
|
||||
|
|
@ -41,16 +44,22 @@ required:
|
|||
|
||||
examples:
|
||||
- |
|
||||
panel {
|
||||
compatible = "visionox,rm69299-1080p-display";
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdda-supply = <&src_pp1800_l8c>;
|
||||
vdd3p3-supply = <&src_pp2800_l18a>;
|
||||
panel@0 {
|
||||
compatible = "visionox,rm69299-1080p-display";
|
||||
reg = <0>;
|
||||
|
||||
reset-gpios = <&pm6150l_gpio 3 0>;
|
||||
port {
|
||||
panel0_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
vdda-supply = <&src_pp1800_l8c>;
|
||||
vdd3p3-supply = <&src_pp2800_l18a>;
|
||||
|
||||
reset-gpios = <&pm6150l_gpio 3 0>;
|
||||
port {
|
||||
panel0_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ properties:
|
|||
unevaluatedProperties: false
|
||||
|
||||
renesas,cmms:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle-array"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
maxItems: 1
|
||||
description:
|
||||
|
|
@ -84,7 +84,7 @@ properties:
|
|||
available DU channel.
|
||||
|
||||
renesas,vsps:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle-array"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle to VSP instance that serves the DU channel
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ properties:
|
|||
description: The number of cells in a MIPI calibration specifier.
|
||||
Should be 1. The single cell specifies a bitmask of the pads that
|
||||
need to be calibrated for a given device.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
const: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
|
|
|||
|
|
@ -69,12 +69,12 @@ properties:
|
|||
# Tegra186 and later
|
||||
nvidia,interface:
|
||||
description: index of the SOR interface
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
nvidia,ddc-i2c-bus:
|
||||
description: phandle of an I2C controller used for DDC EDID
|
||||
probing
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
nvidia,hpd-gpio:
|
||||
description: specifies a GPIO used for hotplug detection
|
||||
|
|
@ -82,23 +82,23 @@ properties:
|
|||
|
||||
nvidia,edid:
|
||||
description: supplies a binary EDID blob
|
||||
$ref: "/schemas/types.yaml#/definitions/uint8-array"
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
|
||||
nvidia,panel:
|
||||
description: phandle of a display panel, required for eDP
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
nvidia,xbar-cfg:
|
||||
description: 5 cells containing the crossbar configuration.
|
||||
Each lane of the SOR, identified by the cell's index, is
|
||||
mapped via the crossbar to the pad specified by the cell's
|
||||
value.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32-array"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
# optional when driving an eDP output
|
||||
nvidia,dpaux:
|
||||
description: phandle to a DispayPort AUX interface
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
|
|
|
|||
|
|
@ -60,13 +60,13 @@ properties:
|
|||
nvidia,outputs:
|
||||
description: A list of phandles of outputs that this display
|
||||
controller can drive.
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle-array"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
|
||||
nvidia,head:
|
||||
description: The number of the display controller head. This
|
||||
is used to setup the various types of output to receive
|
||||
video data from the given head.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ properties:
|
|||
- const: dsi
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/reset/reset.yaml"
|
||||
- $ref: /schemas/reset/reset.yaml
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -59,12 +59,12 @@ properties:
|
|||
description: Should contain a phandle and a specifier specifying
|
||||
which pads are used by this DSI output and need to be
|
||||
calibrated. See nvidia,tegra114-mipi.yaml for details.
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle-array"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
|
||||
nvidia,ddc-i2c-bus:
|
||||
description: phandle of an I2C controller used for DDC EDID
|
||||
probing
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
nvidia,hpd-gpio:
|
||||
description: specifies a GPIO used for hotplug detection
|
||||
|
|
@ -72,19 +72,19 @@ properties:
|
|||
|
||||
nvidia,edid:
|
||||
description: supplies a binary EDID blob
|
||||
$ref: "/schemas/types.yaml#/definitions/uint8-array"
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
|
||||
nvidia,panel:
|
||||
description: phandle of a display panel
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
nvidia,ganged-mode:
|
||||
description: contains a phandle to a second DSI controller to
|
||||
gang up with in order to support up to 8 data lanes
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
allOf:
|
||||
- $ref: "../dsi-controller.yaml#"
|
||||
- $ref: ../dsi-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ properties:
|
|||
nvidia,ddc-i2c-bus:
|
||||
description: phandle of an I2C controller used for DDC EDID
|
||||
probing
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
nvidia,hpd-gpio:
|
||||
description: specifies a GPIO used for hotplug detection
|
||||
|
|
@ -76,11 +76,11 @@ properties:
|
|||
|
||||
nvidia,edid:
|
||||
description: supplies a binary EDID blob
|
||||
$ref: "/schemas/types.yaml#/definitions/uint8-array"
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
|
||||
nvidia,panel:
|
||||
description: phandle of a display panel
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
"#sound-dai-cells":
|
||||
const: 0
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
# Copyright 2019 Texas Instruments Incorporated
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments AM65x Display Subsystem
|
||||
|
||||
|
|
@ -88,7 +88,7 @@ properties:
|
|||
The DSS DPI output port node from video port 2
|
||||
|
||||
ti,am65x-oldi-io-ctrl:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle to syscon device node mapping OLDI IO_CTRL registers.
|
||||
The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
# Copyright 2019 Texas Instruments Incorporated
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments J721E Display Subsystem
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
# Copyright 2019 Texas Instruments Incorporated
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments K2G Display Subsystem
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
# Copyright 2019 Bootlin
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xylon LogiCVC display controller
|
||||
|
||||
|
|
@ -89,25 +89,25 @@ properties:
|
|||
description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
|
||||
|
||||
xylon,display-depth:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Display output depth (C_PIXEL_DATA_WIDTH).
|
||||
|
||||
xylon,row-stride:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE).
|
||||
|
||||
xylon,dithering:
|
||||
$ref: "/schemas/types.yaml#/definitions/flag"
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Dithering module is enabled (C_XCOLOR)
|
||||
|
||||
xylon,background-layer:
|
||||
$ref: "/schemas/types.yaml#/definitions/flag"
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: |
|
||||
The last layer is used to display a black background (C_USE_BACKGROUND).
|
||||
The layer must still be registered.
|
||||
|
||||
xylon,layers-configurable:
|
||||
$ref: "/schemas/types.yaml#/definitions/flag"
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: |
|
||||
Configuration of layers' size, position and offset is enabled
|
||||
(C_USE_SIZE_POSITION).
|
||||
|
|
@ -131,7 +131,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
xylon,layer-depth:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Layer depth (C_LAYER_X_DATA_WIDTH).
|
||||
|
||||
xylon,layer-colorspace:
|
||||
|
|
@ -151,19 +151,19 @@ properties:
|
|||
description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE).
|
||||
|
||||
xylon,layer-base-offset:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Offset in number of lines (C_LAYER_X_OFFSET) starting from the
|
||||
video RAM base (C_VMEM_BASEADDR), only for version 3.
|
||||
|
||||
xylon,layer-buffer-offset:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Offset in number of lines (C_BUFFER_*_OFFSET) starting from the
|
||||
layer base offset for the second buffer used in double-buffering.
|
||||
|
||||
xylon,layer-primary:
|
||||
$ref: "/schemas/types.yaml#/definitions/flag"
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: |
|
||||
Layer should be registered as a primary plane (exactly one is
|
||||
required).
|
||||
|
|
|
|||
|
|
@ -19,12 +19,19 @@ properties:
|
|||
- enum:
|
||||
- amlogic,meson-g12a-mali
|
||||
- mediatek,mt8183-mali
|
||||
- mediatek,mt8183b-mali
|
||||
- mediatek,mt8186-mali
|
||||
- realtek,rtd1619-mali
|
||||
- renesas,r9a07g044-mali
|
||||
- renesas,r9a07g054-mali
|
||||
- rockchip,px30-mali
|
||||
- rockchip,rk3568-mali
|
||||
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-mali
|
||||
- const: mediatek,mt8192-mali
|
||||
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-mali
|
||||
|
|
@ -63,7 +70,11 @@ properties:
|
|||
|
||||
power-domains:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
maxItems: 5
|
||||
|
||||
power-domain-names:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
|
|
@ -93,6 +104,13 @@ properties:
|
|||
|
||||
dma-coherent: true
|
||||
|
||||
nvmem-cell-names:
|
||||
items:
|
||||
- const: speed-bin
|
||||
|
||||
nvmem-cells:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -109,6 +127,10 @@ allOf:
|
|||
contains:
|
||||
const: amlogic,meson-g12a-mali
|
||||
then:
|
||||
properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
power-domain-names: false
|
||||
required:
|
||||
- resets
|
||||
- if:
|
||||
|
|
@ -131,6 +153,9 @@ allOf:
|
|||
- const: gpu
|
||||
- const: bus
|
||||
- const: bus_ace
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
power-domain-names: false
|
||||
resets:
|
||||
minItems: 3
|
||||
reset-names:
|
||||
|
|
@ -152,6 +177,7 @@ allOf:
|
|||
properties:
|
||||
power-domains:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: core0
|
||||
|
|
@ -164,9 +190,61 @@ allOf:
|
|||
- power-domain-names
|
||||
else:
|
||||
properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
sram-supply: false
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8183b-mali
|
||||
then:
|
||||
properties:
|
||||
power-domains:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: core0
|
||||
- const: core1
|
||||
- const: core2
|
||||
required:
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8186-mali
|
||||
then:
|
||||
properties:
|
||||
power-domains:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: core0
|
||||
- const: core1
|
||||
required:
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8192-mali
|
||||
then:
|
||||
properties:
|
||||
power-domains:
|
||||
minItems: 5
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: core0
|
||||
- const: core1
|
||||
- const: core2
|
||||
- const: core3
|
||||
- const: core4
|
||||
required:
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -180,6 +258,9 @@ allOf:
|
|||
items:
|
||||
- const: gpu
|
||||
- const: bus
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
power-domain-names: false
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
|
|
|
|||
|
|
@ -313,7 +313,7 @@ imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl)
|
|||
}
|
||||
|
||||
/* specially select the next bridge with companion PXL2DPI */
|
||||
if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL))
|
||||
if (of_property_present(remote, "fsl,companion-pxl2dpi"))
|
||||
bridge_sel = ep_cnt;
|
||||
|
||||
ep_cnt++;
|
||||
|
|
|
|||
|
|
@ -258,12 +258,12 @@
|
|||
#define REG_AUD_INFOFRAM_SUM 0xFB
|
||||
|
||||
/* the following six registers are in bank1 */
|
||||
#define REG_DRV_0_DB_800_MV 0x7E
|
||||
#define REG_PRE_0_DB_800_MV 0x7F
|
||||
#define REG_PRE_3P5_DB_800_MV 0x81
|
||||
#define REG_SSC_CTRL0 0x88
|
||||
#define REG_SSC_CTRL1 0x89
|
||||
#define REG_SSC_CTRL2 0x8A
|
||||
#define REG_DRV_0_DB_800_MV 0x17E
|
||||
#define REG_PRE_0_DB_800_MV 0x17F
|
||||
#define REG_PRE_3P5_DB_800_MV 0x181
|
||||
#define REG_SSC_CTRL0 0x188
|
||||
#define REG_SSC_CTRL1 0x189
|
||||
#define REG_SSC_CTRL2 0x18A
|
||||
|
||||
#define RBR DP_LINK_BW_1_62
|
||||
#define HBR DP_LINK_BW_2_7
|
||||
|
|
@ -489,7 +489,7 @@ static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
|
|||
};
|
||||
|
||||
static const struct regmap_range it6505_bridge_volatile_ranges[] = {
|
||||
{ .range_min = 0, .range_max = 0xFF },
|
||||
{ .range_min = 0, .range_max = 0x1FF },
|
||||
};
|
||||
|
||||
static const struct regmap_access_table it6505_bridge_volatile_table = {
|
||||
|
|
@ -497,11 +497,27 @@ static const struct regmap_access_table it6505_bridge_volatile_table = {
|
|||
.n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
|
||||
};
|
||||
|
||||
static const struct regmap_range_cfg it6505_regmap_banks[] = {
|
||||
{
|
||||
.name = "it6505",
|
||||
.range_min = 0x00,
|
||||
.range_max = 0x1FF,
|
||||
.selector_reg = REG_BANK_SEL,
|
||||
.selector_mask = 0x1,
|
||||
.selector_shift = 0,
|
||||
.window_start = 0x00,
|
||||
.window_len = 0x100,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct regmap_config it6505_regmap_config = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.volatile_table = &it6505_bridge_volatile_table,
|
||||
.cache_type = REGCACHE_NONE,
|
||||
.ranges = it6505_regmap_banks,
|
||||
.num_ranges = ARRAY_SIZE(it6505_regmap_banks),
|
||||
.max_register = 0x1FF,
|
||||
};
|
||||
|
||||
static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
|
||||
|
|
@ -1267,7 +1283,6 @@ static void it6505_init(struct it6505 *it6505)
|
|||
it6505_write(it6505, REG_TIME_STMP_CTRL,
|
||||
EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
|
||||
it6505_write(it6505, REG_INFOFRAME_CTRL, 0x00);
|
||||
it6505_write(it6505, REG_BANK_SEL, 0x01);
|
||||
it6505_write(it6505, REG_DRV_0_DB_800_MV,
|
||||
afe_setting_table[it6505->afe_setting][0]);
|
||||
it6505_write(it6505, REG_PRE_0_DB_800_MV,
|
||||
|
|
@ -1277,7 +1292,6 @@ static void it6505_init(struct it6505 *it6505)
|
|||
it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
|
||||
it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
|
||||
it6505_write(it6505, REG_SSC_CTRL2, 0x42);
|
||||
it6505_write(it6505, REG_BANK_SEL, 0x00);
|
||||
}
|
||||
|
||||
static void it6505_video_disable(struct it6505 *it6505)
|
||||
|
|
@ -1506,11 +1520,9 @@ static void it6505_setup_ssc(struct it6505 *it6505)
|
|||
it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
|
||||
it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
|
||||
if (it6505->enable_ssc) {
|
||||
it6505_write(it6505, REG_BANK_SEL, 0x01);
|
||||
it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
|
||||
it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
|
||||
it6505_write(it6505, REG_SSC_CTRL2, 0x42);
|
||||
it6505_write(it6505, REG_BANK_SEL, 0x00);
|
||||
it6505_write(it6505, REG_SP_CTRL0, 0x07);
|
||||
it6505_write(it6505, REG_IP_CTRL1, 0x29);
|
||||
it6505_write(it6505, REG_IP_CTRL2, 0x03);
|
||||
|
|
|
|||
|
|
@ -496,7 +496,7 @@ static int ps8622_probe(struct i2c_client *client)
|
|||
ps8622->lane_count = ps8622->max_lane_count;
|
||||
}
|
||||
|
||||
if (!of_find_property(dev->of_node, "use-external-pwm", NULL)) {
|
||||
if (!of_property_read_bool(dev->of_node, "use-external-pwm")) {
|
||||
ps8622->bl = backlight_device_register("ps8622-backlight",
|
||||
dev, ps8622, &ps8622_backlight_ops,
|
||||
NULL);
|
||||
|
|
|
|||
|
|
@ -105,6 +105,7 @@ struct ps8640 {
|
|||
struct gpio_desc *gpio_reset;
|
||||
struct gpio_desc *gpio_powerdown;
|
||||
struct device_link *link;
|
||||
struct edid *edid;
|
||||
bool pre_enabled;
|
||||
bool need_post_hpd_delay;
|
||||
};
|
||||
|
|
@ -542,34 +543,44 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
|
|||
struct drm_connector *connector)
|
||||
{
|
||||
struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
|
||||
struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
|
||||
bool poweroff = !ps_bridge->pre_enabled;
|
||||
struct edid *edid;
|
||||
|
||||
/*
|
||||
* When we end calling get_edid() triggered by an ioctl, i.e
|
||||
*
|
||||
* drm_mode_getconnector (ioctl)
|
||||
* -> drm_helper_probe_single_connector_modes
|
||||
* -> drm_bridge_connector_get_modes
|
||||
* -> ps8640_bridge_get_edid
|
||||
*
|
||||
* We need to make sure that what we need is enabled before reading
|
||||
* EDID, for this chip, we need to do a full poweron, otherwise it will
|
||||
* fail.
|
||||
*/
|
||||
drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state);
|
||||
if (!ps_bridge->edid) {
|
||||
/*
|
||||
* When we end calling get_edid() triggered by an ioctl, i.e
|
||||
*
|
||||
* drm_mode_getconnector (ioctl)
|
||||
* -> drm_helper_probe_single_connector_modes
|
||||
* -> drm_bridge_connector_get_modes
|
||||
* -> ps8640_bridge_get_edid
|
||||
*
|
||||
* We need to make sure that what we need is enabled before
|
||||
* reading EDID, for this chip, we need to do a full poweron,
|
||||
* otherwise it will fail.
|
||||
*/
|
||||
if (poweroff)
|
||||
drm_atomic_bridge_chain_pre_enable(bridge,
|
||||
connector->state->state);
|
||||
|
||||
edid = drm_get_edid(connector,
|
||||
ps_bridge->page[PAGE0_DP_CNTL]->adapter);
|
||||
ps_bridge->edid = drm_get_edid(connector,
|
||||
ps_bridge->page[PAGE0_DP_CNTL]->adapter);
|
||||
|
||||
/*
|
||||
* If we call the get_edid() function without having enabled the chip
|
||||
* before, return the chip to its original power state.
|
||||
*/
|
||||
if (poweroff)
|
||||
drm_atomic_bridge_chain_post_disable(bridge, connector->state->state);
|
||||
/*
|
||||
* If we call the get_edid() function without having enabled the
|
||||
* chip before, return the chip to its original power state.
|
||||
*/
|
||||
if (poweroff)
|
||||
drm_atomic_bridge_chain_post_disable(bridge,
|
||||
connector->state->state);
|
||||
}
|
||||
|
||||
return edid;
|
||||
if (!ps_bridge->edid) {
|
||||
dev_err(dev, "Failed to get EDID\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return drm_edid_duplicate(ps_bridge->edid);
|
||||
}
|
||||
|
||||
static void ps8640_runtime_disable(void *data)
|
||||
|
|
@ -766,6 +777,13 @@ static int ps8640_probe(struct i2c_client *client)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void ps8640_remove(struct i2c_client *client)
|
||||
{
|
||||
struct ps8640 *ps_bridge = i2c_get_clientdata(client);
|
||||
|
||||
kfree(ps_bridge->edid);
|
||||
}
|
||||
|
||||
static const struct of_device_id ps8640_match[] = {
|
||||
{ .compatible = "parade,ps8640" },
|
||||
{ }
|
||||
|
|
@ -774,6 +792,7 @@ MODULE_DEVICE_TABLE(of, ps8640_match);
|
|||
|
||||
static struct i2c_driver ps8640_driver = {
|
||||
.probe_new = ps8640_probe,
|
||||
.remove = ps8640_remove,
|
||||
.driver = {
|
||||
.name = "ps8640",
|
||||
.of_match_table = ps8640_match,
|
||||
|
|
|
|||
|
|
@ -329,7 +329,7 @@ int mipi_dsi_host_register(struct mipi_dsi_host *host)
|
|||
|
||||
for_each_available_child_of_node(host->dev->of_node, node) {
|
||||
/* skip nodes without reg property */
|
||||
if (!of_find_property(node, "reg", NULL))
|
||||
if (!of_property_present(node, "reg"))
|
||||
continue;
|
||||
of_mipi_dsi_device_add(host, node);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -964,7 +964,7 @@ static void adreno_get_pwrlevels(struct device *dev,
|
|||
gpu->fast_rate = 0;
|
||||
|
||||
/* You down with OPP? */
|
||||
if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
|
||||
if (!of_property_present(dev->of_node, "operating-points-v2"))
|
||||
ret = adreno_get_legacy_pwrlevels(dev);
|
||||
else {
|
||||
ret = devm_pm_opp_of_add_table(dev);
|
||||
|
|
|
|||
|
|
@ -1871,6 +1871,7 @@ static const struct edp_panel_entry edp_panels[] = {
|
|||
EDP_PANEL_ENTRY('A', 'U', 'O', 0x1e9b, &delay_200_500_e50, "B133UAN02.1"),
|
||||
EDP_PANEL_ENTRY('A', 'U', 'O', 0x1ea5, &delay_200_500_e50, "B116XAK01.6"),
|
||||
EDP_PANEL_ENTRY('A', 'U', 'O', 0x405c, &auo_b116xak01.delay, "B116XAK01"),
|
||||
EDP_PANEL_ENTRY('A', 'U', 'O', 0x582d, &delay_200_500_e50, "B133UAN01.0"),
|
||||
EDP_PANEL_ENTRY('A', 'U', 'O', 0x615c, &delay_200_500_e50, "B116XAN06.1"),
|
||||
EDP_PANEL_ENTRY('A', 'U', 'O', 0x8594, &delay_200_500_e50, "B133UAN01.0"),
|
||||
|
||||
|
|
|
|||
|
|
@ -418,7 +418,7 @@ static int d53e6ea8966_probe(struct spi_device *spi)
|
|||
if (IS_ERR(db->dsi_dev)) {
|
||||
dev_err(dev, "failed to register dsi device: %ld\n",
|
||||
PTR_ERR(db->dsi_dev));
|
||||
ret = PTR_ERR(db->dsi_dev);
|
||||
return PTR_ERR(db->dsi_dev);
|
||||
}
|
||||
|
||||
db->dsi_dev->lanes = 2;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/devfreq.h>
|
||||
#include <linux/devfreq_cooling.h>
|
||||
#include <linux/nvmem-consumer.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_opp.h>
|
||||
|
||||
|
|
@ -82,6 +83,31 @@ static struct devfreq_dev_profile panfrost_devfreq_profile = {
|
|||
.get_dev_status = panfrost_devfreq_get_dev_status,
|
||||
};
|
||||
|
||||
static int panfrost_read_speedbin(struct device *dev)
|
||||
{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = nvmem_cell_read_variable_le_u32(dev, "speed-bin", &val);
|
||||
if (ret) {
|
||||
/*
|
||||
* -ENOENT means that this platform doesn't support speedbins
|
||||
* as it didn't declare any speed-bin nvmem: in this case, we
|
||||
* keep going without it; any other error means that we are
|
||||
* supposed to read the bin value, but we failed doing so.
|
||||
*/
|
||||
if (ret != -ENOENT) {
|
||||
DRM_DEV_ERROR(dev, "Cannot read speed-bin (%d).", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
DRM_DEV_DEBUG(dev, "Using speed-bin = 0x%x\n", val);
|
||||
|
||||
return devm_pm_opp_set_supported_hw(dev, &val, 1);
|
||||
}
|
||||
|
||||
int panfrost_devfreq_init(struct panfrost_device *pfdev)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -101,6 +127,10 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
ret = panfrost_read_speedbin(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_pm_opp_set_regulators(dev, pfdev->comp->supply_names);
|
||||
if (ret) {
|
||||
/* Continue if the optional regulator is missing */
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ struct panfrost_job;
|
|||
struct panfrost_perfcnt;
|
||||
|
||||
#define NUM_JOB_SLOTS 3
|
||||
#define MAX_PM_DOMAINS 3
|
||||
#define MAX_PM_DOMAINS 5
|
||||
|
||||
struct panfrost_features {
|
||||
u16 id;
|
||||
|
|
|
|||
|
|
@ -647,6 +647,14 @@ static const struct panfrost_compatible amlogic_data = {
|
|||
.vendor_quirk = panfrost_gpu_amlogic_quirk,
|
||||
};
|
||||
|
||||
/*
|
||||
* The old data with two power supplies for MT8183 is here only to
|
||||
* keep retro-compatibility with older devicetrees, as DVFS will
|
||||
* not work with this one.
|
||||
*
|
||||
* On new devicetrees please use the _b variant with a single and
|
||||
* coupled regulators instead.
|
||||
*/
|
||||
static const char * const mediatek_mt8183_supplies[] = { "mali", "sram", NULL };
|
||||
static const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "core2" };
|
||||
static const struct panfrost_compatible mediatek_mt8183_data = {
|
||||
|
|
@ -656,6 +664,32 @@ static const struct panfrost_compatible mediatek_mt8183_data = {
|
|||
.pm_domain_names = mediatek_mt8183_pm_domains,
|
||||
};
|
||||
|
||||
static const char * const mediatek_mt8183_b_supplies[] = { "mali", NULL };
|
||||
static const struct panfrost_compatible mediatek_mt8183_b_data = {
|
||||
.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
|
||||
.supply_names = mediatek_mt8183_b_supplies,
|
||||
.num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
|
||||
.pm_domain_names = mediatek_mt8183_pm_domains,
|
||||
};
|
||||
|
||||
static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" };
|
||||
static const struct panfrost_compatible mediatek_mt8186_data = {
|
||||
.num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1,
|
||||
.supply_names = mediatek_mt8183_b_supplies,
|
||||
.num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),
|
||||
.pm_domain_names = mediatek_mt8186_pm_domains,
|
||||
};
|
||||
|
||||
static const char * const mediatek_mt8192_supplies[] = { "mali", NULL };
|
||||
static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2",
|
||||
"core3", "core4" };
|
||||
static const struct panfrost_compatible mediatek_mt8192_data = {
|
||||
.num_supplies = ARRAY_SIZE(mediatek_mt8192_supplies) - 1,
|
||||
.supply_names = mediatek_mt8192_supplies,
|
||||
.num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains),
|
||||
.pm_domain_names = mediatek_mt8192_pm_domains,
|
||||
};
|
||||
|
||||
static const struct of_device_id dt_match[] = {
|
||||
/* Set first to probe before the generic compatibles */
|
||||
{ .compatible = "amlogic,meson-gxm-mali",
|
||||
|
|
@ -674,6 +708,9 @@ static const struct of_device_id dt_match[] = {
|
|||
{ .compatible = "arm,mali-bifrost", .data = &default_data, },
|
||||
{ .compatible = "arm,mali-valhall-jm", .data = &default_data, },
|
||||
{ .compatible = "mediatek,mt8183-mali", .data = &mediatek_mt8183_data },
|
||||
{ .compatible = "mediatek,mt8183b-mali", .data = &mediatek_mt8183_b_data },
|
||||
{ .compatible = "mediatek,mt8186-mali", .data = &mediatek_mt8186_data },
|
||||
{ .compatible = "mediatek,mt8192-mali", .data = &mediatek_mt8192_data },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dt_match);
|
||||
|
|
|
|||
|
|
@ -204,6 +204,14 @@ static const struct panfrost_model gpu_models[] = {
|
|||
|
||||
GPU_MODEL(g57, 0x9001,
|
||||
GPU_REV(g57, 0, 0)),
|
||||
|
||||
/* MediaTek MT8192 has a Mali-G57 with a different GPU ID from the
|
||||
* standard. Arm's driver does not appear to handle this model.
|
||||
* ChromeOS has a hack downstream for it. Treat it as equivalent to
|
||||
* standard Mali-G57 for now.
|
||||
*/
|
||||
GPU_MODEL(g57, 0x9003,
|
||||
GPU_REV(g57, 0, 0)),
|
||||
};
|
||||
|
||||
static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
|
||||
|
|
|
|||
|
|
@ -722,7 +722,7 @@ EXPORT_SYMBOL(drm_sched_job_add_dependency);
|
|||
/**
|
||||
* drm_sched_job_add_syncobj_dependency - adds a syncobj's fence as a job dependency
|
||||
* @job: scheduler job to add the dependencies to
|
||||
* @file_private: drm file private pointer
|
||||
* @file: drm file private pointer
|
||||
* @handle: syncobj handle to lookup
|
||||
* @point: timeline point
|
||||
*
|
||||
|
|
|
|||
|
|
@ -792,7 +792,7 @@ static int sun4i_backend_bind(struct device *dev, struct device *master,
|
|||
dev_set_drvdata(dev, backend);
|
||||
spin_lock_init(&backend->frontend_lock);
|
||||
|
||||
if (of_find_property(dev->of_node, "interconnects", NULL)) {
|
||||
if (of_property_present(dev->of_node, "interconnects")) {
|
||||
/*
|
||||
* This assume we have the same DMA constraints for all our the
|
||||
* devices in our pipeline (all the backends, but also the
|
||||
|
|
|
|||
|
|
@ -391,7 +391,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
|
|||
mixer->engine.ops = &sun8i_engine_ops;
|
||||
mixer->engine.node = dev->of_node;
|
||||
|
||||
if (of_find_property(dev->of_node, "iommus", NULL)) {
|
||||
if (of_property_present(dev->of_node, "iommus")) {
|
||||
/*
|
||||
* This assume we have the same DMA constraints for
|
||||
* all our the mixers in our pipeline. This sounds
|
||||
|
|
|
|||
|
|
@ -162,13 +162,9 @@ static bool display_get_big_endian_of(struct drm_device *dev, struct device_node
|
|||
bool big_endian;
|
||||
|
||||
#ifdef __BIG_ENDIAN
|
||||
big_endian = true;
|
||||
if (of_get_property(of_node, "little-endian", NULL))
|
||||
big_endian = false;
|
||||
big_endian = !of_property_read_bool(of_node, "little-endian");
|
||||
#else
|
||||
big_endian = false;
|
||||
if (of_get_property(of_node, "big-endian", NULL))
|
||||
big_endian = true;
|
||||
big_endian = of_property_read_bool(of_node, "big-endian");
|
||||
#endif
|
||||
|
||||
return big_endian;
|
||||
|
|
|
|||
|
|
@ -204,7 +204,7 @@ simplefb_get_memory_of(struct drm_device *dev, struct device_node *of_node)
|
|||
if (err)
|
||||
return ERR_PTR(err);
|
||||
|
||||
if (of_get_property(of_node, "reg", NULL))
|
||||
if (of_property_present(of_node, "reg"))
|
||||
drm_warn(dev, "preferring \"memory-region\" over \"reg\" property\n");
|
||||
|
||||
return res;
|
||||
|
|
|
|||
|
|
@ -3020,7 +3020,7 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
|
|||
struct device *dev = &pdev->dev;
|
||||
int ret;
|
||||
|
||||
if (!of_find_property(dev->of_node, "interrupts", NULL)) {
|
||||
if (!of_property_present(dev->of_node, "interrupts")) {
|
||||
dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user