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KVM VMX changes for 7.3
- Service local TLB flushes on a failed nested VM-Enter to fix a bug where KVM
could miss a TLB on a future, successful VM-Enter with the same L2 VPID.
- Cap the maximum value shoved into the VMX Preemption Timer to workaround an
erratum that affects all existing Intel CPUs that support CPUID 0x15.
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Merge tag 'kvm-x86-vmx-7.3' of https://github.com/kvm-x86/linux into HEAD
KVM VMX changes for 7.3
- Service local TLB flushes on a failed nested VM-Enter to fix a bug where KVM
could miss a TLB on a future, successful VM-Enter with the same L2 VPID.
- Cap the maximum value shoved into the VMX Preemption Timer to workaround an
erratum that affects all existing Intel CPUs that support CPUID 0x15.
This commit is contained in:
Paolo Bonzini
commit
634c347df1
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@ -3759,6 +3759,14 @@ enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
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vmentry_fail_vmexit_guest_mode:
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if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
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vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
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/*
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* Handle any TLB flush requests that were queued for L2 if KVM made it
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* far enough along to switch to L2 context. Note, loading host state
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* will generate any flushes for L1 required by VM-Exit.
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*/
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kvm_service_local_tlb_flush_requests(vcpu);
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leave_guest_mode(vcpu);
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vmentry_fail_vmexit:
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@ -150,10 +150,13 @@ module_param(dump_invalid_vmcs, bool, 0644);
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#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
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/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
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#ifdef CONFIG_X86_64
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static int __read_mostly cpu_preemption_timer_multi;
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static bool __read_mostly enable_preemption_timer = 1;
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#ifdef CONFIG_X86_64
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static u64 __ro_after_init preemption_timer_max_value;
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module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
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#else
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#define enable_preemption_timer false
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#endif
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extern bool __read_mostly allow_smaller_maxphyaddr;
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@ -2159,7 +2162,7 @@ int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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!guest_has_spec_ctrl_msr(vcpu))
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return 1;
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msr_info->data = to_vmx(vcpu)->spec_ctrl;
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msr_info->data = vmx->spec_ctrl;
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break;
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case MSR_IA32_SYSENTER_CS:
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msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
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@ -2191,7 +2194,7 @@ int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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if (!msr_info->host_initiated &&
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!guest_cpu_cap_has(vcpu, X86_FEATURE_SGX_LC))
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return 1;
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msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
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msr_info->data = vmx->msr_ia32_sgxlepubkeyhash
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[msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
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break;
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case KVM_FIRST_EMULATED_VMX_MSR ... KVM_LAST_EMULATED_VMX_MSR:
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@ -2404,7 +2407,7 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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vmx_guest_debugctl_write(vcpu, data);
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if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
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if (intel_pmu_lbr_is_enabled(vcpu) && !vmx->lbr_desc.event &&
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(data & DEBUGCTLMSR_LBR))
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intel_pmu_create_guest_lbr_event(vcpu);
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return 0;
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@ -2483,7 +2486,7 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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break;
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case MSR_IA32_MCG_EXT_CTL:
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if ((!msr_info->host_initiated &&
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!(to_vmx(vcpu)->msr_ia32_feature_control &
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!(vmx->msr_ia32_feature_control &
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FEAT_CTL_LMCE_ENABLED)) ||
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(data & ~MCG_EXT_CTL_LMCE_EN))
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return 1;
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@ -3678,13 +3681,14 @@ void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
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u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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struct kvm_segment s;
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if (to_vmx(vcpu)->rmode.vm86_active) {
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if (vmx->rmode.vm86_active) {
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vmx_get_segment(vcpu, &s, seg);
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return s.base;
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}
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return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
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return vmx_read_guest_seg_base(vmx, seg);
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}
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static int __vmx_get_cpl(struct kvm_vcpu *vcpu, bool no_cache)
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@ -7407,32 +7411,6 @@ static void vmx_refresh_guest_perf_global_control(struct kvm_vcpu *vcpu)
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pmu->global_ctrl = vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL);
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}
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static void vmx_update_hv_timer(struct kvm_vcpu *vcpu, bool force_immediate_exit)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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u64 tscl;
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u32 delta_tsc;
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if (force_immediate_exit) {
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vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
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vmx->loaded_vmcs->hv_timer_soft_disabled = false;
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} else if (vmx->hv_deadline_tsc != -1) {
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tscl = rdtsc();
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if (vmx->hv_deadline_tsc > tscl)
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/* set_hv_timer ensures the delta fits in 32-bits */
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delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
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cpu_preemption_timer_multi);
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else
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delta_tsc = 0;
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vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
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vmx->loaded_vmcs->hv_timer_soft_disabled = false;
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} else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
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vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
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vmx->loaded_vmcs->hv_timer_soft_disabled = true;
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}
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}
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void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
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{
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if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
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@ -7518,6 +7496,8 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
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guest_state_exit_irqoff();
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}
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static void vmx_update_hv_timer(struct kvm_vcpu *vcpu, bool force_immediate_exit);
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fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu, u64 run_flags)
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{
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bool force_immediate_exit = run_flags & KVM_RUN_FORCE_IMMEDIATE_EXIT;
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@ -8330,6 +8310,65 @@ static inline int u64_shl_div_u64(u64 a, unsigned int shift,
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return 0;
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}
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/*
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* Workaround for a widespread Intel erratum (e.g. EMR158) where the
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* VMX-preemption timer may expire earlier than expected when programmed
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* with large values. The workaround is to cap the timer value to strictly
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* less than 2^25 * CPUID.15H:EBX / CPUID.15H:EAX.
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*/
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static __init u64 calc_preemption_timer_max_value(void)
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{
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const u64 ARCHITECTURAL_MAX_VALUE = UINT_MAX;
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u32 eax, ebx, ecx, edx;
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if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
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return ARCHITECTURAL_MAX_VALUE;
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if (cpuid_eax(0) < 0x15)
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return ARCHITECTURAL_MAX_VALUE;
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cpuid(0x15, &eax, &ebx, &ecx, &edx);
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if (!eax || !ebx)
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return ARCHITECTURAL_MAX_VALUE;
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if (WARN_ON_ONCE(!(((u64)ebx << 25) / eax)))
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return ARCHITECTURAL_MAX_VALUE;
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return min((((u64)ebx << 25) / eax) - 1, ARCHITECTURAL_MAX_VALUE);
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}
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static __init void vmx_setup_preemption_timer(void)
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{
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if (!cpu_has_vmx_preemption_timer())
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enable_preemption_timer = false;
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if (enable_preemption_timer) {
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u64 use_timer_freq = 5000ULL * 1000 * 1000;
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cpu_preemption_timer_multi =
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vmx_misc_preemption_timer_rate(vmcs_config.misc);
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preemption_timer_max_value = calc_preemption_timer_max_value();
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if (tsc_khz)
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use_timer_freq = (u64)tsc_khz * 1000;
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use_timer_freq >>= cpu_preemption_timer_multi;
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/*
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* KVM "disables" the preemption timer by setting it to its max
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* value. Don't use the timer if it might cause spurious exits
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* at a rate faster than 0.1 Hz (of uninterrupted guest time).
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*/
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if (use_timer_freq > preemption_timer_max_value / 10)
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enable_preemption_timer = false;
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}
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if (!enable_preemption_timer) {
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vt_x86_ops.set_hv_timer = NULL;
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vt_x86_ops.cancel_hv_timer = NULL;
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}
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}
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int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
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bool *expired)
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{
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@ -8357,12 +8396,12 @@ int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
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return -ERANGE;
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/*
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* If the delta tsc can't fit in the 32 bit after the multi shift,
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* we can't use the preemption timer.
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* If the delta tsc exceeds the preemption timer limit after the
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* multi shift, we can't use the preemption timer.
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* It's possible that it fits on later vmentries, but checking
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* on every vmentry is costly so we just use an hrtimer.
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*/
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if (delta_tsc >> (cpu_preemption_timer_multi + 32))
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if ((delta_tsc >> cpu_preemption_timer_multi) > preemption_timer_max_value)
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return -ERANGE;
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vmx->hv_deadline_tsc = tscl + delta_tsc;
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@ -8374,6 +8413,39 @@ void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
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{
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to_vmx(vcpu)->hv_deadline_tsc = -1;
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}
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static void vmx_update_hv_timer(struct kvm_vcpu *vcpu, bool force_immediate_exit)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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u64 tscl;
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u32 delta_tsc;
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if (force_immediate_exit) {
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vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
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vmx->loaded_vmcs->hv_timer_soft_disabled = false;
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} else if (vmx->hv_deadline_tsc != -1) {
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tscl = rdtsc();
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if (vmx->hv_deadline_tsc > tscl)
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/* set_hv_timer ensures the delta fits in 32-bits */
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delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
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cpu_preemption_timer_multi);
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else
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delta_tsc = 0;
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vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
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vmx->loaded_vmcs->hv_timer_soft_disabled = false;
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} else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
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vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preemption_timer_max_value);
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vmx->loaded_vmcs->hv_timer_soft_disabled = true;
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}
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}
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#else
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static __init void vmx_setup_preemption_timer(void) { }
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static void vmx_update_hv_timer(struct kvm_vcpu *vcpu, bool force_immediate_exit)
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{
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BUILD_BUG_ON(1);
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}
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#endif
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void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
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@ -8736,32 +8808,7 @@ __init int vmx_hardware_setup(void)
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if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
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enable_pml = 0;
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if (!cpu_has_vmx_preemption_timer())
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enable_preemption_timer = false;
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if (enable_preemption_timer) {
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u64 use_timer_freq = 5000ULL * 1000 * 1000;
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cpu_preemption_timer_multi =
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vmx_misc_preemption_timer_rate(vmcs_config.misc);
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if (tsc_khz)
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use_timer_freq = (u64)tsc_khz * 1000;
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use_timer_freq >>= cpu_preemption_timer_multi;
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/*
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* KVM "disables" the preemption timer by setting it to its max
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* value. Don't use the timer if it might cause spurious exits
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* at a rate faster than 0.1 Hz (of uninterrupted guest time).
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*/
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if (use_timer_freq > 0xffffffffu / 10)
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enable_preemption_timer = false;
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}
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if (!enable_preemption_timer) {
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vt_x86_ops.set_hv_timer = NULL;
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vt_x86_ops.cancel_hv_timer = NULL;
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}
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vmx_setup_preemption_timer();
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kvm_caps.supported_mce_cap |= MCG_LMCE_P;
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kvm_caps.supported_mce_cap |= MCG_CMCI_P;
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