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arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags

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The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.

Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and
OSPI NOR Flash.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Wadim Egorov 2025-03-05 09:55:33 +01:00 committed by Vignesh Raghavendra
parent ce553288ad
commit 63426153ef
2 changed files with 24 additions and 0 deletions
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15
arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
View File

@ -29,6 +29,7 @@ aliases {
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
bootph-all;
};
reserved_memory: reserved-memory {
@ -137,6 +138,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
bootph-all;
};
main_mdio1_pins_default: main-mdio1-default-pins {
@ -144,6 +146,7 @@ main_mdio1_pins_default: main-mdio1-default-pins {
AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
>;
bootph-all;
};
main_mmc0_pins_default: main-mmc0-default-pins {
@ -159,6 +162,7 @@ AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
>;
bootph-all;
};
main_rgmii1_pins_default: main-rgmii1-default-pins {
@ -176,6 +180,7 @@ AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
>;
bootph-all;
};
ospi0_pins_default: ospi0-default-pins {
@ -192,6 +197,7 @@ AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
>;
bootph-all;
};
pmic_irq_pins_default: pmic-irq-default-pins {
@ -216,6 +222,7 @@ &cpsw3g {
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
bootph-all;
};
&cpsw3g_mdio {
@ -226,6 +233,7 @@ &cpsw3g_mdio {
cpsw3g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <1>;
bootph-all;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
@ -238,10 +246,15 @@ mbox_m4_0: mbox-m4-0 {
};
};
&main_pktdma {
bootph-all;
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
bootph-all;
status = "okay";
pmic@30 {
@ -361,6 +374,7 @@ serial_flash: flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
bootph-all;
};
};
@ -369,5 +383,6 @@ &sdhci0 {
pinctrl-0 = <&main_mmc0_pins_default>;
disable-wp;
non-removable;
bootph-all;
status = "okay";
};

9
arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
View File

@ -138,6 +138,7 @@ vcc_3v3_mmc: regulator-vcc-3v3-mmc {
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
bootph-all;
};
vcc_3v3_sw: regulator-vcc-3v3-sw {
@ -233,6 +234,7 @@ AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */
AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
>;
bootph-all;
};
main_rgmii2_pins_default: main-rgmii2-default-pins {
@ -257,6 +259,7 @@ main_uart0_pins_default: main-uart0-default-pins {
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
>;
bootph-all;
};
main_uart1_pins_default: main-uart1-default-pins {
@ -266,6 +269,7 @@ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
>;
bootph-pre-ram;
};
main_usb1_pins_default: main-usb1-default-pins {
@ -430,12 +434,14 @@ &main_mcan0 {
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
bootph-all;
status = "okay";
};
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
bootph-pre-ram;
/* Main UART1 may be used by TIFS firmware */
status = "okay";
};
@ -467,11 +473,13 @@ &sdhci1 {
pinctrl-0 = <&main_mmc1_pins_default>;
disable-wp;
no-1-8-v;
bootph-all;
status = "okay";
};
&usbss0 {
ti,vbus-divider;
bootph-all;
status = "okay";
};
@ -482,6 +490,7 @@ &usbss1 {
&usb0 {
usb-role-switch;
bootph-all;
port {
typec_hs: endpoint {