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- add D1 CAN bus gates and resets

Browse Source 
- mark D1 CPUX clock as critical
 - reuse D1 driver for R528/T113
 - cleanup sunxi-ng kconfig
 - fix sunxi-ng kernel-doc issues
 - model H3/H5 DRAM clock as fixed clock
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Merge tag 'sunxi-clk-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Jernej Skrabec:

 - add D1 CAN bus gates and resets
 - mark D1 CPUX clock as critical
 - reuse D1 driver for R528/T113
 - cleanup sunxi-ng kconfig
 - fix sunxi-ng kernel-doc issues
 - model H3/H5 DRAM clock as fixed clock

* tag 'sunxi-clk-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: d1: Add CAN bus gates and resets
  dt-bindings: clock: Add D1 CAN bus gates and resets
  clk: sunxi-ng: d1: Mark cpux clock as critical
  clk: sunxi-ng: d1: Allow building for R528/T113
  clk: sunxi-ng: Move SoC driver conditions to dependencies
  clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependencies
  clk: sunxi-ng: Avoid computing the rate twice
  clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock
  clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issues
This commit is contained in:
Stephen Boyd 2023-01-30 15:31:03 -08:00
commit 633ff55419
12 changed files with 93 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
drivers/clk/sunxi-ng/Kconfig
View File

@ -9,112 +9,113 @@ if SUNXI_CCU
config SUNIV_F1C100S_CCU
tristate "Support for the Allwinner newer F1C100s CCU"
default MACH_SUNIV
default y
depends on MACH_SUNIV || COMPILE_TEST
config SUN20I_D1_CCU
tristate "Support for the Allwinner D1 CCU"
default RISCV && ARCH_SUNXI
depends on (RISCV && ARCH_SUNXI) || COMPILE_TEST
tristate "Support for the Allwinner D1/R528/T113 CCU"
default y
depends on MACH_SUN8I || RISCV || COMPILE_TEST
config SUN20I_D1_R_CCU
tristate "Support for the Allwinner D1 PRCM CCU"
default RISCV && ARCH_SUNXI
depends on (RISCV && ARCH_SUNXI) || COMPILE_TEST
tristate "Support for the Allwinner D1/R528/T113 PRCM CCU"
default y
depends on MACH_SUN8I || RISCV || COMPILE_TEST
config SUN50I_A64_CCU
tristate "Support for the Allwinner A64 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
default y
depends on ARM64 || COMPILE_TEST
config SUN50I_A100_CCU
tristate "Support for the Allwinner A100 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
default y
depends on ARM64 || COMPILE_TEST
config SUN50I_A100_R_CCU
tristate "Support for the Allwinner A100 PRCM CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
default y
depends on ARM64 || COMPILE_TEST
config SUN50I_H6_CCU
tristate "Support for the Allwinner H6 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
default y
depends on ARM64 || COMPILE_TEST
config SUN50I_H616_CCU
tristate "Support for the Allwinner H616 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
default y
depends on ARM64 || COMPILE_TEST
config SUN50I_H6_R_CCU
tristate "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
default y
depends on ARM64 || COMPILE_TEST
config SUN4I_A10_CCU
tristate "Support for the Allwinner A10/A20 CCU"
default MACH_SUN4I
default MACH_SUN7I
default y
depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
config SUN5I_CCU
bool "Support for the Allwinner sun5i family CCM"
default MACH_SUN5I
default y
depends on MACH_SUN5I || COMPILE_TEST
depends on SUNXI_CCU=y
config SUN6I_A31_CCU
tristate "Support for the Allwinner A31/A31s CCU"
default MACH_SUN6I
default y
depends on MACH_SUN6I || COMPILE_TEST
config SUN6I_RTC_CCU
tristate "Support for the Allwinner H616/R329 RTC CCU"
default ARCH_SUNXI
depends on ARCH_SUNXI || COMPILE_TEST
default y
depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
config SUN8I_A23_CCU
tristate "Support for the Allwinner A23 CCU"
default MACH_SUN8I
default y
depends on MACH_SUN8I || COMPILE_TEST
config SUN8I_A33_CCU
tristate "Support for the Allwinner A33 CCU"
default MACH_SUN8I
default y
depends on MACH_SUN8I || COMPILE_TEST
config SUN8I_A83T_CCU
tristate "Support for the Allwinner A83T CCU"
default MACH_SUN8I
default y
depends on MACH_SUN8I || COMPILE_TEST
config SUN8I_H3_CCU
tristate "Support for the Allwinner H3 CCU"
default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
default y
depends on MACH_SUN8I || ARM64 || COMPILE_TEST
config SUN8I_V3S_CCU
tristate "Support for the Allwinner V3s CCU"
default MACH_SUN8I
default y
depends on MACH_SUN8I || COMPILE_TEST
config SUN8I_DE2_CCU
tristate "Support for the Allwinner SoCs DE2 CCU"
default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
default y
depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
config SUN8I_R40_CCU
tristate "Support for the Allwinner R40 CCU"
default MACH_SUN8I
default y
depends on MACH_SUN8I || COMPILE_TEST
config SUN9I_A80_CCU
tristate "Support for the Allwinner A80 CCU"
default MACH_SUN9I
default y
depends on MACH_SUN9I || COMPILE_TEST
config SUN8I_R_CCU
tristate "Support for Allwinner SoCs' PRCM CCUs"
default MACH_SUN8I || (ARCH_SUNXI && ARM64)
default y
depends on MACH_SUN8I || ARM64 || COMPILE_TEST
endif

13
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
View File

@ -240,7 +240,7 @@ static const struct clk_parent_data cpux_parents[] = {
{ .hw = &pll_periph0_800M_clk.common.hw },
};
static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents,
0x500, 24, 3, CLK_SET_RATE_PARENT);
0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };
static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",
@ -469,6 +469,11 @@ static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
0x91c, BIT(3), 0);
static SUNXI_CCU_GATE_HWS(bus_can0_clk, "bus-can0", apb1_hws,
0x92c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_can1_clk, "bus-can1", apb1_hws,
0x92c, BIT(1), 0);
static const struct clk_parent_data spi_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_periph0_clk.hw },
@ -997,6 +1002,8 @@ static struct ccu_common *sun20i_d1_ccu_clks[] = {
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_i2c3_clk.common,
&bus_can0_clk.common,
&bus_can1_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&bus_spi0_clk.common,
@ -1147,6 +1154,8 @@ static struct clk_hw_onecell_data sun20i_d1_hw_clks = {
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
[CLK_BUS_CAN0] = &bus_can0_clk.common.hw,
[CLK_BUS_CAN1] = &bus_can1_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
@ -1252,6 +1261,8 @@ static struct ccu_reset_map sun20i_d1_ccu_resets[] = {
[RST_BUS_I2C1] = { 0x91c, BIT(17) },
[RST_BUS_I2C2] = { 0x91c, BIT(18) },
[RST_BUS_I2C3] = { 0x91c, BIT(19) },
[RST_BUS_CAN0] = { 0x92c, BIT(16) },
[RST_BUS_CAN1] = { 0x92c, BIT(17) },
[RST_BUS_SPI0] = { 0x96c, BIT(16) },
[RST_BUS_SPI1] = { 0x96c, BIT(17) },
[RST_BUS_EMAC] = { 0x97c, BIT(16) },

2
drivers/clk/sunxi-ng/ccu-sun20i-d1.h
View File

@ -10,6 +10,6 @@
#include <dt-bindings/clock/sun20i-d1-ccu.h>
#include <dt-bindings/reset/sun20i-d1-ccu.h>
#define CLK_NUMBER (CLK_FANOUT2 + 1)
#define CLK_NUMBER (CLK_BUS_CAN1 + 1)
#endif /* _CCU_SUN20I_D1_H_ */

15
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
View File

@ -434,8 +434,13 @@ static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc24M",
0x0cc, BIT(19), 0);
static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
/* H3 has broken MDFS hardware, so the mux/divider cannot be changed. */
static CLK_FIXED_FACTOR_HW(h3_dram_clk, "dram",
&pll_ddr_clk.common.hw,
1, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static const char * const h5_dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX(h5_dram_clk, "dram", h5_dram_parents,
0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
@ -592,7 +597,7 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = {
&usb_ohci1_clk.common,
&usb_ohci2_clk.common,
&usb_ohci3_clk.common,
&dram_clk.common,
&h5_dram_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&dram_deinterlace_clk.common,
@ -732,7 +737,7 @@ static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
[CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_DRAM] = &h3_dram_clk.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
@ -848,7 +853,7 @@ static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
[CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_DRAM] = &h5_dram_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,

8
drivers/clk/sunxi-ng/ccu_mmc_timing.c
View File

@ -10,11 +10,11 @@
#include "ccu_common.h"
/**
* sunxi_ccu_set_mmc_timing_mode: Configure the MMC clock timing mode
* sunxi_ccu_set_mmc_timing_mode - Configure the MMC clock timing mode
* @clk: clock to be configured
* @new_mode: true for new timing mode introduced in A83T and later
*
* Returns 0 on success, -ENOTSUPP if the clock does not support
* Return: %0 on success, %-ENOTSUPP if the clock does not support
* switching modes.
*/
int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode)
@ -46,8 +46,8 @@ EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode);
* sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode
* @clk: clock to query
*
* Returns 0 if the clock is in old timing mode, > 0 if it is in
* new timing mode, and -ENOTSUPP if the clock does not support
* Return: %0 if the clock is in old timing mode, > %0 if it is in
* new timing mode, and %-ENOTSUPP if the clock does not support
* this function.
*/
int sunxi_ccu_get_mmc_timing_mode(struct clk *clk)

11
drivers/clk/sunxi-ng/ccu_mp.c
View File

@ -10,9 +10,9 @@
#include "ccu_gate.h"
#include "ccu_mp.h"
static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
unsigned int max_m, unsigned int max_p,
unsigned int *m, unsigned int *p)
static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
unsigned int max_m, unsigned int max_p,
unsigned int *m, unsigned int *p)
{
unsigned long best_rate = 0;
unsigned int best_m = 0, best_p = 0;
@ -35,6 +35,8 @@ static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
*m = best_m;
*p = best_p;
return best_rate;
}
static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
@ -109,8 +111,7 @@ static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
rate = *parent_rate / p / m;
rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
} else {
rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
max_m, max_p);

9
drivers/clk/sunxi-ng/ccu_nk.c
View File

@ -15,8 +15,8 @@ struct _ccu_nk {
unsigned long k, min_k, max_k;
};
static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nk *nk)
static unsigned long ccu_nk_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nk *nk)
{
unsigned long best_rate = 0;
unsigned int best_k = 0, best_n = 0;
@ -39,6 +39,8 @@ static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
nk->k = best_k;
nk->n = best_n;
return best_rate;
}
static void ccu_nk_disable(struct clk_hw *hw)
@ -104,8 +106,7 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
_nk.min_k = nk->k.min ?: 1;
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
ccu_nk_find_best(*parent_rate, rate, &_nk);
rate = *parent_rate * _nk.n * _nk.k;
rate = ccu_nk_find_best(*parent_rate, rate, &_nk);
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate / nk->fixed_post_div;

10
drivers/clk/sunxi-ng/ccu_nkm.c
View File

@ -16,8 +16,8 @@ struct _ccu_nkm {
unsigned long m, min_m, max_m;
};
static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nkm *nkm)
static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nkm *nkm)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_k = 0, best_m = 0;
@ -45,6 +45,8 @@ static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
nkm->n = best_n;
nkm->k = best_k;
nkm->m = best_m;
return best_rate;
}
static void ccu_nkm_disable(struct clk_hw *hw)
@ -122,9 +124,7 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nkm->fixed_post_div;
ccu_nkm_find_best(*parent_rate, rate, &_nkm);
rate = *parent_rate * _nkm.n * _nkm.k / _nkm.m;
rate = ccu_nkm_find_best(*parent_rate, rate, &_nkm);
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nkm->fixed_post_div;

10
drivers/clk/sunxi-ng/ccu_nkmp.c
View File

@ -29,8 +29,8 @@ static unsigned long ccu_nkmp_calc_rate(unsigned long parent,
return rate;
}
static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nkmp *nkmp)
static unsigned long ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nkmp *nkmp)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
@ -65,6 +65,8 @@ static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
nkmp->k = best_k;
nkmp->m = best_m;
nkmp->p = best_p;
return best_rate;
}
static void ccu_nkmp_disable(struct clk_hw *hw)
@ -150,10 +152,8 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
_nkmp.min_p = 1;
_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
rate = ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
rate = ccu_nkmp_calc_rate(*parent_rate, _nkmp.n, _nkmp.k,
_nkmp.m, _nkmp.p);
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate / nkmp->fixed_post_div;

9
drivers/clk/sunxi-ng/ccu_nm.c
View File

@ -27,8 +27,8 @@ static unsigned long ccu_nm_calc_rate(unsigned long parent,
return rate;
}
static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nm *nm)
static unsigned long ccu_nm_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nm *nm)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_m = 0;
@ -52,6 +52,8 @@ static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
nm->n = best_n;
nm->m = best_m;
return best_rate;
}
static void ccu_nm_disable(struct clk_hw *hw)
@ -157,8 +159,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
_nm.min_m = 1;
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
ccu_nm_find_best(*parent_rate, rate, &_nm);
rate = ccu_nm_calc_rate(*parent_rate, _nm.n, _nm.m);
rate = ccu_nm_find_best(*parent_rate, rate, &_nm);
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;

2
include/dt-bindings/clock/sun20i-d1-ccu.h
View File

@ -152,5 +152,7 @@
#define CLK_FANOUT0 142
#define CLK_FANOUT1 143
#define CLK_FANOUT2 144
#define CLK_BUS_CAN0 145
#define CLK_BUS_CAN1 146
#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */

2
include/dt-bindings/reset/sun20i-d1-ccu.h
View File

@ -73,5 +73,7 @@
#define RST_BUS_DSP_CFG 63
#define RST_BUS_DSP_DBG 64
#define RST_BUS_RISCV_CFG 65
#define RST_BUS_CAN0 66
#define RST_BUS_CAN1 67
#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */