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This pull request contains Broadcom ARM-based SoCs changes for 5.10,
please pull the following: - Florian adds debug UART entries for the 72164 and 72165 SoCs and updates ARCH_BRCMSTB to select CONFIG_BCM7038_L1_IRQ which is an interrupt controller used with the 7211 chip family -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl9Zj+EACgkQh9CWnEQH BwR5KxAAueGJLtUleVHLKKTdCDmrTSwklDB0bFDHaQjTJc8KEp2VuT4X9B7Il0lh sNOsP1vFUO2Y9yZGn7FXIkTbDyiILPCuu7zfo7dWHC91X/qPqVbeYDcsWz1/EUX5 OTNAERKgLiEFpgyA3dpCvTTTE7I/aTFaie+ZYbHvFXAJ6wrTP08Xli/igTxomXeB sGSPkwHJWPthcrNU9DvukNYH1BtmuSOVgFiDzFIaoTyWdX12omoErLVwfNiXRL3J 1RkhcXZNN23xG9a020NbJhdUFHtsIKzaKK8CGUr7fwblvZGRbyyD7wy73nF5ZVlw SPb5CW21GCwJ/WjEfDU2ocXYZVQykS79NswWHHv8VM2K5mLb/N2ad+ebKol5wbds TOzgrtEty1DnQa7ukswUllgRkIFvq4aoeOVUe2K1Z2y090pmrdCjGW67WsFzGzFK yANvpI0T0nvUY1ZhMroKUgAYJ9H/123ruBCTLty6F3zDNFSAPP5w51hRYgiU26Fb IC/2PFGWtVI7tOtGwKRz3KoHRwknj0CK7/dI47dGI3vBViuEMqVlKQ+xwu4MMrlC E1A/Nv9TqMaFKA6sZEMmmVJxnUbDEHJ0h+B7vglBbaSM545BIOi1dYuzSrkELESH r2TjMAry/T5LxJyBZJGDZ5nz/O34jfA2cW2ouQ3TJDTQb6m7agw= =4cWQ -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-5.10/soc' of https://github.com/Broadcom/stblinux into arm/soc This pull request contains Broadcom ARM-based SoCs changes for 5.10, please pull the following: - Florian adds debug UART entries for the 72164 and 72165 SoCs and updates ARCH_BRCMSTB to select CONFIG_BCM7038_L1_IRQ which is an interrupt controller used with the 7211 chip family * tag 'arm-soc/for-5.10/soc' of https://github.com/Broadcom/stblinux: ARM: brcmstb: Add debug UART entry for 72615 ARM: bcm: Enable BCM7038_L1_IRQ for ARCH_BRCMSTB ARM: brcmstb: Add debug UART entry for 72614 Link: https://lore.kernel.org/r/20200912032153.1216354-5-f.fainelli@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
632db90624
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@ -32,6 +32,8 @@
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#define UARTA_7271 UARTA_7268
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#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
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#define UARTA_7216 UARTA_7278
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#define UARTA_72164 UARTA_7278
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#define UARTA_72165 UARTA_7278
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#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
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#define UARTA_7366 UARTA_7364
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#define UARTA_74371 REG_PHYS_ADDR(0x406b00)
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@ -84,17 +86,19 @@ ARM_BE8( rev \rv, \rv )
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/* Chip specific detection starts here */
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20: checkuart(\rp, \rv, 0x33900000, 3390)
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21: checkuart(\rp, \rv, 0x72160000, 7216)
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22: checkuart(\rp, \rv, 0x72500000, 7250)
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23: checkuart(\rp, \rv, 0x72550000, 7255)
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24: checkuart(\rp, \rv, 0x72600000, 7260)
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25: checkuart(\rp, \rv, 0x72680000, 7268)
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26: checkuart(\rp, \rv, 0x72710000, 7271)
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27: checkuart(\rp, \rv, 0x72780000, 7278)
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28: checkuart(\rp, \rv, 0x73640000, 7364)
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29: checkuart(\rp, \rv, 0x73660000, 7366)
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30: checkuart(\rp, \rv, 0x07437100, 74371)
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31: checkuart(\rp, \rv, 0x74390000, 7439)
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32: checkuart(\rp, \rv, 0x74450000, 7445)
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22: checkuart(\rp, \rv, 0x07216400, 72164)
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23: checkuart(\rp, \rv, 0x07216500, 72165)
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24: checkuart(\rp, \rv, 0x72500000, 7250)
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25: checkuart(\rp, \rv, 0x72550000, 7255)
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26: checkuart(\rp, \rv, 0x72600000, 7260)
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27: checkuart(\rp, \rv, 0x72680000, 7268)
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28: checkuart(\rp, \rv, 0x72710000, 7271)
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29: checkuart(\rp, \rv, 0x72780000, 7278)
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30: checkuart(\rp, \rv, 0x73640000, 7364)
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31: checkuart(\rp, \rv, 0x73660000, 7366)
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32: checkuart(\rp, \rv, 0x07437100, 74371)
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33: checkuart(\rp, \rv, 0x74390000, 7439)
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34: checkuart(\rp, \rv, 0x74450000, 7445)
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/* No valid UART found */
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90: mov \rp, #0
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@ -208,6 +208,7 @@ config ARCH_BRCMSTB
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select ARM_GIC
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select ARM_ERRATA_798181 if SMP
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select HAVE_ARM_ARCH_TIMER
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select BCM7038_L1_IRQ
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select BRCMSTB_L2_IRQ
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select BCM7120_L2_IRQ
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select ARCH_HAS_HOLES_MEMORYMODEL
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