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drm/msm/a6xx: Allow IFPC with perfcntr stream

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Now that the dynamic pwrup reglist has SEL reg values to restore
appended, so that SEL regs are restored on IFPC exit, we can stop
completely disabling IFPC while global counter sampling is active.

To accomplish this, we re-use sysprof_setup() with a force_on param
to inhibit IFPC specifically while the counter regs are being read,
while leaving IFPC enabled the rest of the time.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728219/
Message-ID: <20260526145137.160554-17-robin.clark@oss.qualcomm.com>
This commit is contained in:
Rob Clark 2026-05-26 07:50:50 -07:00
parent 45d4a295b3
commit 632ad55101
5 changed files with 14 additions and 12 deletions
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4
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View File

@ -2078,9 +2078,9 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
return irq;
}
void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu)
void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on)
{
bool sysprof = msm_gpu_sysprof_no_ifpc(gpu);
bool sysprof = msm_gpu_sysprof_no_ifpc(gpu) || force_on;
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
View File

@ -281,7 +281,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu);
void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on);
void a6xx_preempt_init(struct msm_gpu *gpu);
void a6xx_preempt_hw_init(struct msm_gpu *gpu);

10
drivers/gpu/drm/msm/msm_gpu.h
View File

@ -93,7 +93,7 @@ struct msm_gpu_funcs {
* for cmdstream that is buffered in this FIFO upstream of the CP fw.
*/
bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
void (*sysprof_setup)(struct msm_gpu *gpu);
void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on);
/* Configure perfcntr SELect regs: */
void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
@ -378,13 +378,7 @@ msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu)
static inline bool
msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu)
{
/*
* For now, this is the same condition as disabling perfcntr clears
* on context switch. But once kernel perfcntr IFPC support is in
* place, we will only need to disable IFPC for legacy userspace
* setting SYSPROF param.
*/
return msm_gpu_sysprof_no_perfcntr_zap(gpu);
return refcount_read(&gpu->sysprof_active) > 1;
}
/*

8
drivers/gpu/drm/msm/msm_perfcntr.c
View File

@ -258,6 +258,10 @@ sample_worker(struct kthread_work *work)
return;
}
/* Inhibit IFPC while accessing registers: */
if (gpu->funcs->sysprof_setup)
gpu->funcs->sysprof_setup(gpu, true);
if (gpu->funcs->perfcntr_flush)
gpu->funcs->perfcntr_flush(gpu);
@ -292,6 +296,10 @@ sample_worker(struct kthread_work *work)
}
}
/* Re-enable IFPC: */
if (gpu->funcs->sysprof_setup)
gpu->funcs->sysprof_setup(gpu, false);
smp_store_release(&stream->fifo.head, head);
wake_up_all(&stream->poll_wq);
}

2
drivers/gpu/drm/msm/msm_submitqueue.c
View File

@ -42,7 +42,7 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy
/* Some gpu families require additional setup for sysprof */
if (gpu->funcs->sysprof_setup)
gpu->funcs->sysprof_setup(gpu);
gpu->funcs->sysprof_setup(gpu, false);
ctx->sysprof = sysprof;