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Minor improvements in ARM64 DTS for v6.10

Browse Source 
Fixes, which might have practical impact, however things were broken for
 long enough to justify pushing it regular path:
 1. ARM Juno: shorten node names for thermal zones, because Linux drivers
    have strict limit of 20 characters.
 2. HiSilicon: correct size of GIC GICC address space and add missing
    GICH and GICV spaces, add cache info to properly describe cache
    topology and solve kernel boot warning.
 
 Several cleanups:
 1. Use capital "OR" for multiple licenses in SPDX.
 2. Correct white-spaces for code readability.
 3. Fix W=1 dtc compiler warnings, which should not have practical
    impact for Amazon, APM, Cavium, Realtek, Socionext Uniphier and
    Spreadtrum like:
     - missing unit addresses,
     - nodes not belonging to soc node,
     - not using generic node names,
     - few incorrect unit addresses.
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Merge tag 'dt64-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

Minor improvements in ARM64 DTS for v6.10

Fixes, which might have practical impact, however things were broken for
long enough to justify pushing it regular path:
1. ARM Juno: shorten node names for thermal zones, because Linux drivers
   have strict limit of 20 characters.
2. HiSilicon: correct size of GIC GICC address space and add missing
   GICH and GICV spaces, add cache info to properly describe cache
   topology and solve kernel boot warning.

Several cleanups:
1. Use capital "OR" for multiple licenses in SPDX.
2. Correct white-spaces for code readability.
3. Fix W=1 dtc compiler warnings, which should not have practical
   impact for Amazon, APM, Cavium, Realtek, Socionext Uniphier and
   Spreadtrum like:
    - missing unit addresses,
    - nodes not belonging to soc node,
    - not using generic node names,
    - few incorrect unit addresses.

* tag 'dt64-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: (28 commits)
  arm64: dts: cavium: thunder2-99xx: drop redundant reg-names
  arm64: dts: amazon: alpine-v3: correct gic unit addresses
  arm64: dts: amazon: alpine-v3: drop cache nodes unit addresses
  arm64: dts: amazon: alpine-v3: add missing io-fabric unit addresses
  arm64: dts: amazon: alpine-v2: move non-MMIO node out of soc
  arm64: dts: amazon: alpine-v2: add missing io-fabric unit addresses
  arm64: dts: apm: shadowcat: move non-MMIO node out of soc
  arm64: dts: apm: storm: move non-MMIO node out of soc
  arm64: dts: cavium: correct unit addresses
  arm64: dts: cavium: move non-MMIO node out of soc
  arm64: dts: realtek: rtc16xx: add missing unit address to soc node
  arm64: dts: realtek: rtd139x: add missing unit address to soc node
  arm64: dts: realtek: rtd129x: add missing unit address to soc node
  arm64: dts: uniphier: ld20-global: drop audio codec port unit address
  arm64: dts: uniphier: ld20-global: use generic node name for audio-codec
  arm64: dts: uniphier: ld11-global: drop audio codec port unit address
  arm64: dts: uniphier: ld11-global: use generic node name for audio-codec
  arm64: dts: sharkl3: add missing unit addresses
  arm64: dts: whale2: add missing ap-apb unit address
  arm64: dts: sc9860: move GIC to soc node
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-04-29 18:12:53 +02:00
commit 631ec37483
23 changed files with 159 additions and 117 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
arch/arm64/boot/dts/amazon/alpine-v2.dtsi
View File

@ -39,6 +39,7 @@
/ {
model = "Annapurna Labs Alpine v2";
compatible = "al,alpine-v2";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@ -89,6 +90,22 @@ sbclk: sbclk {
clock-frequency = <1000000>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@ -97,22 +114,6 @@ soc {
interrupt-parent = <&gic>;
ranges;
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@f0200000 {
compatible = "arm,gic-v3";
reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */
@ -150,7 +151,7 @@ msix: msix@fbe00000 {
al,msi-num-spis = <160>;
};
io-fabric {
io-fabric@fc000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

12
arch/arm64/boot/dts/amazon/alpine-v3.dtsi
View File

@ -244,7 +244,7 @@ cpu@303 {
next-level-cache = <&cluster3_l2>;
};
cluster0_l2: cache@0 {
cluster0_l2: cache-0 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
@ -253,7 +253,7 @@ cluster0_l2: cache@0 {
cache-unified;
};
cluster1_l2: cache@100 {
cluster1_l2: cache-100 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
@ -262,7 +262,7 @@ cluster1_l2: cache@100 {
cache-unified;
};
cluster2_l2: cache@200 {
cluster2_l2: cache-200 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
@ -271,7 +271,7 @@ cluster2_l2: cache@200 {
cache-unified;
};
cluster3_l2: cache@300 {
cluster3_l2: cache-300 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
@ -318,7 +318,7 @@ soc {
#size-cells = <2>;
ranges;
gic: interrupt-controller@f0000000 {
gic: interrupt-controller@f0800000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
@ -361,7 +361,7 @@ msix: msix@fbe00000 {
interrupt-parent = <&gic>;
};
io-fabric {
io-fabric@fc000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm64/boot/dts/amd/elba-16core.dtsi
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright 2020-2023 Advanced Micro Devices, Inc.
*/

2
arch/arm64/boot/dts/amd/elba-asic-common.dtsi
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright 2020-2022 Advanced Micro Devices, Inc.
*/

2
arch/arm64/boot/dts/amd/elba-asic.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree file for AMD Pensando Elba Board.
*

2
arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright 2020-2023 Advanced Micro Devices, Inc.
*/

2
arch/arm64/boot/dts/amd/elba.dtsi
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright 2020-2022 Advanced Micro Devices, Inc.
*/

14
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View File

@ -211,6 +211,13 @@ v2m15: v2m@f0000 {
};
};
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <100000000>;
clock-output-names = "refclk";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <1 12 0xff04>;
@ -236,13 +243,6 @@ clocks {
#size-cells = <2>;
ranges;
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <100000000>;
clock-output-names = "refclk";
};
pmdpll: pmdpll@170000f0 {
compatible = "apm,xgene-pcppll-v2-clock";
#clock-cells = <1>;

13
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -112,6 +112,13 @@ gic: interrupt-controller@78010000 {
interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
};
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <100000000>;
clock-output-names = "refclk";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
@ -137,12 +144,6 @@ clocks {
#address-cells = <2>;
#size-cells = <2>;
ranges;
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <100000000>;
clock-output-names = "refclk";
};
pcppll: pcppll@17000100 {
compatible = "apm,xgene-pcppll-clock";

4
arch/arm64/boot/dts/arm/juno-base.dtsi
View File

@ -773,14 +773,14 @@ soc_crit0: trip0 {
};
};
big_cluster_thermal_zone: big-cluster-thermal {
big_cluster_thermal_zone: big-cl-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 21>;
status = "disabled";
};
little_cluster_thermal_zone: little-cluster-thermal {
little_cluster_thermal_zone: little-cl-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 22>;

4
arch/arm64/boot/dts/arm/juno-scmi.dtsi
View File

@ -84,11 +84,11 @@ soc-thermal {
thermal-sensors = <&scmi_sensors0 3>;
};
big-cluster-thermal {
big-cl-thermal {
thermal-sensors = <&scmi_sensors0 21>;
};
little-cluster-thermal {
little-cl-thermal {
thermal-sensors = <&scmi_sensors0 22>;
};

20
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
View File

@ -365,20 +365,20 @@ pmu {
interrupts = <1 7 4>;
};
refclk50mhz: refclk50mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "refclk50mhz";
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
refclk50mhz: refclk50mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "refclk50mhz";
};
gic0: interrupt-controller@8010,00000000 {
gic0: interrupt-controller@801000000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
@ -397,7 +397,7 @@ its: msi-controller@801000020000 {
};
};
uaa0: serial@87e0,24000000 {
uaa0: serial@87e024000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x24000000 0x0 0x1000>;
interrupts = <1 21 4>;
@ -405,7 +405,7 @@ uaa0: serial@87e0,24000000 {
clock-names = "apb_pclk";
};
uaa1: serial@87e0,25000000 {
uaa1: serial@87e025000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x25000000 0x0 0x1000>;
interrupts = <1 22 4>;

1
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
View File

@ -103,7 +103,6 @@ pcie@30000000 {
/* ECAM at 0x3000_0000 - 0x4000_0000 */
reg = <0x0 0x30000000 0x0 0x10000000>;
reg-names = "PCI ECAM";
/*
* PCI ranges:

43
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
View File

@ -31,6 +31,13 @@ cpu@0 {
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-size = <0x8000>; /* 32 KiB */
d-cache-line-size = <64>;
d-cache-sets = <128>;
i-cache-size = <0x8000>; /* 32 KiB */
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&L2>;
};
cpu@1 {
@ -38,6 +45,13 @@ cpu@1 {
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-size = <0x8000>; /* 32 KiB */
d-cache-line-size = <64>;
d-cache-sets = <128>;
i-cache-size = <0x8000>; /* 32 KiB */
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&L2>;
};
cpu@2 {
@ -45,6 +59,13 @@ cpu@2 {
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
d-cache-size = <0x8000>; /* 32 KiB */
d-cache-line-size = <64>;
d-cache-sets = <128>;
i-cache-size = <0x8000>; /* 32 KiB */
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&L2>;
};
cpu@3 {
@ -52,13 +73,33 @@ cpu@3 {
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
d-cache-size = <0x8000>; /* 32 KiB */
d-cache-line-size = <64>;
d-cache-sets = <128>;
i-cache-size = <0x8000>; /* 32 KiB */
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&L2>;
};
};
L2: l2-cache {
compatible = "cache";
cache-unified;
cache-size = <0x80000>; /* 512 KiB */
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
<0x0 0xf1002000 0x0 0x100>; /* GICC */
<0x0 0xf1002000 0x0 0x2000>, /* GICC */
<0x0 0xf1004000 0x0 0x2000>, /* GICH */
<0x0 0xf1006000 0x0 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;

2
arch/arm64/boot/dts/realtek/rtd129x.dtsi
View File

@ -48,7 +48,7 @@ osc27M: osc {
clock-output-names = "osc27M";
};
soc {
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm64/boot/dts/realtek/rtd139x.dtsi
View File

@ -47,7 +47,7 @@ osc27M: osc {
clock-output-names = "osc27M";
};
soc {
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm64/boot/dts/realtek/rtd16xx.dtsi
View File

@ -127,7 +127,7 @@ osc27M: osc {
#clock-cells = <0>;
};
soc {
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

4
arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
View File

@ -111,7 +111,7 @@ &comp_spdif_hiecout1 {
&i2c0 {
status = "okay";
tas5707a@1d {
audio-codec@1d {
compatible = "ti,tas5711";
reg = <0x1d>;
reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>;
@ -124,7 +124,7 @@ tas5707a@1d {
PVDD_C-supply = <&amp_vcc_reg>;
PVDD_D-supply = <&amp_vcc_reg>;
port@0 {
port {
tas_speaker: endpoint {
dai-format = "i2s";
remote-endpoint = <&i2s_hpcmout1>;

4
arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
View File

@ -111,7 +111,7 @@ &comp_spdif_hiecout1 {
&i2c0 {
status = "okay";
tas5707@1b {
audio-codec@1b {
compatible = "ti,tas5711";
reg = <0x1b>;
reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>;
@ -124,7 +124,7 @@ tas5707@1b {
PVDD_C-supply = <&amp_vcc_reg>;
PVDD_D-supply = <&amp_vcc_reg>;
port@0 {
port {
tas_speaker: endpoint {
dai-format = "i2s";
remote-endpoint = <&i2s_hpcmout1>;

56
arch/arm64/boot/dts/sprd/sc9860.dtsi
View File

@ -113,7 +113,7 @@ CPU7: cpu@530103 {
};
};
idle-states{
idle-states {
entry-method = "psci";
CORE_PD: core_pd {
@ -135,18 +135,6 @@ CLUSTER_PD: cluster_pd {
};
};
gic: interrupt-controller@12001000 {
compatible = "arm,gic-400";
reg = <0 0x12001000 0 0x1000>,
<0 0x12002000 0 0x2000>,
<0 0x12004000 0 0x2000>,
<0 0x12006000 0 0x2000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
@ -185,6 +173,18 @@ pmu {
};
soc {
gic: interrupt-controller@12001000 {
compatible = "arm,gic-400";
reg = <0 0x12001000 0 0x1000>,
<0 0x12002000 0 0x2000>,
<0 0x12004000 0 0x2000>,
<0 0x12006000 0 0x2000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_HIGH)>;
};
pmu_gate: pmu-gate {
compatible = "sprd,sc9860-pmu-gate";
sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
@ -207,7 +207,7 @@ ap_clk: clock-controller@20000000 {
#clock-cells = <1>;
};
aon_prediv: aon-prediv {
aon_prediv: aon-prediv@402d0000 {
compatible = "sprd,sc9860-aon-prediv";
reg = <0 0x402d0000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>,
@ -684,33 +684,5 @@ etm7_out: endpoint {
};
};
};
gpio-keys {
compatible = "gpio-keys";
key-volumedown {
label = "Volume Down Key";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>;
debounce-interval = <2>;
wakeup-source;
};
key-volumeup {
label = "Volume Up Key";
linux,code = <KEY_VOLUMEUP>;
gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>;
debounce-interval = <2>;
wakeup-source;
};
key-power {
label = "Power Key";
linux,code = <KEY_POWER>;
gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>;
debounce-interval = <2>;
wakeup-source;
};
};
};
};

18
arch/arm64/boot/dts/sprd/sharkl3.dtsi
View File

@ -24,7 +24,7 @@ ap_ahb_regs: syscon@20e00000 {
#size-cells = <1>;
ranges = <0 0 0x20e00000 0x4000>;
apahb_gate: apahb-gate {
apahb_gate: apahb-gate@0 {
compatible = "sprd,sc9863a-apahb-gate";
reg = <0x0 0x1020>;
#clock-cells = <1>;
@ -39,7 +39,7 @@ pmu_regs: syscon@402b0000 {
#size-cells = <1>;
ranges = <0 0 0x402b0000 0x4000>;
pmu_gate: pmu-gate {
pmu_gate: pmu-gate@0 {
compatible = "sprd,sc9863a-pmu-gate";
reg = <0 0x1200>;
clocks = <&ext_26m>;
@ -56,7 +56,7 @@ aon_apb_regs: syscon@402e0000 {
#size-cells = <1>;
ranges = <0 0 0x402e0000 0x4000>;
aonapb_gate: aonapb-gate {
aonapb_gate: aonapb-gate@0 {
compatible = "sprd,sc9863a-aonapb-gate";
reg = <0 0x1100>;
#clock-cells = <1>;
@ -71,7 +71,7 @@ anlg_phy_g2_regs: syscon@40353000 {
#size-cells = <1>;
ranges = <0 0 0x40353000 0x3000>;
pll: pll {
pll: pll@0 {
compatible = "sprd,sc9863a-pll";
reg = <0 0x100>;
clocks = <&ext_26m>;
@ -88,7 +88,7 @@ anlg_phy_g4_regs: syscon@40359000 {
#size-cells = <1>;
ranges = <0 0 0x40359000 0x3000>;
mpll: mpll {
mpll: mpll@0 {
compatible = "sprd,sc9863a-mpll";
reg = <0 0x100>;
#clock-cells = <1>;
@ -103,7 +103,7 @@ anlg_phy_g5_regs: syscon@4035c000 {
#size-cells = <1>;
ranges = <0 0 0x4035c000 0x3000>;
rpll: rpll {
rpll: rpll@0 {
compatible = "sprd,sc9863a-rpll";
reg = <0 0x100>;
clocks = <&ext_26m>;
@ -120,7 +120,7 @@ anlg_phy_g7_regs: syscon@40363000 {
#size-cells = <1>;
ranges = <0 0 0x40363000 0x3000>;
dpll: dpll {
dpll: dpll@0 {
compatible = "sprd,sc9863a-dpll";
reg = <0 0x100>;
#clock-cells = <1>;
@ -135,7 +135,7 @@ mm_ahb_regs: syscon@60800000 {
#size-cells = <1>;
ranges = <0 0 0x60800000 0x3000>;
mm_gate: mm-gate {
mm_gate: mm-gate@0 {
compatible = "sprd,sc9863a-mm-gate";
reg = <0 0x1100>;
#clock-cells = <1>;
@ -150,7 +150,7 @@ ap_apb_regs: syscon@71300000 {
#size-cells = <1>;
ranges = <0 0 0x71300000 0x4000>;
apapb_gate: apapb-gate {
apapb_gate: apapb-gate@0 {
compatible = "sprd,sc9863a-apapb-gate";
reg = <0 0x1000>;
clocks = <&ext_26m>;

30
arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
View File

@ -24,7 +24,7 @@ aliases {
spi0 = &adi_bus;
};
memory{
memory {
device_type = "memory";
reg = <0x0 0x80000000 0 0x60000000>,
<0x1 0x80000000 0 0x60000000>;
@ -34,6 +34,34 @@ chosen {
stdout-path = "serial1:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
key-volumedown {
label = "Volume Down Key";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>;
debounce-interval = <2>;
wakeup-source;
};
key-volumeup {
label = "Volume Up Key";
linux,code = <KEY_VOLUMEUP>;
gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>;
debounce-interval = <2>;
wakeup-source;
};
key-power {
label = "Power Key";
linux,code = <KEY_POWER>;
gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>;
debounce-interval = <2>;
wakeup-source;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;

2
arch/arm64/boot/dts/sprd/whale2.dtsi
View File

@ -64,7 +64,7 @@ ap_apb_regs: syscon@70b00000 {
reg = <0 0x70b00000 0 0x40000>;
};
ap-apb {
ap-apb@70000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;