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drm/amdgpu/gfx9: replace BUG_ON() with WARN_ON()
There's no need to crash the kernel for these cases. Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit b71604f8685b0eba07866f4e8dc30f93e1931054) Cc: stable@vger.kernel.org
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@ -1183,7 +1183,7 @@ static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
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WAIT_REG_MEM_ENGINE(eng_sel)));
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if (mem_space)
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BUG_ON(addr0 & 0x3); /* Dword align */
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WARN_ON(addr0 & 0x3); /* Dword align */
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amdgpu_ring_write(ring, addr0);
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amdgpu_ring_write(ring, addr1);
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amdgpu_ring_write(ring, ref);
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@ -5474,7 +5474,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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}
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amdgpu_ring_write(ring, header);
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BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
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WARN_ON(ib->gpu_addr & 0x3); /* Dword align */
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amdgpu_ring_write(ring,
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#ifdef __BIG_ENDIAN
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(2 << 0) |
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@ -5570,7 +5570,7 @@ static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
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}
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amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
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WARN_ON(ib->gpu_addr & 0x3); /* Dword align */
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amdgpu_ring_write(ring,
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#ifdef __BIG_ENDIAN
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(2 << 0) |
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@ -5611,9 +5611,9 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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* aligned if only send 32bit data low (discard data high)
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*/
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if (write64bit)
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BUG_ON(addr & 0x7);
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WARN_ON(addr & 0x7);
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else
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BUG_ON(addr & 0x3);
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WARN_ON(addr & 0x3);
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amdgpu_ring_write(ring, lower_32_bits(addr));
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amdgpu_ring_write(ring, upper_32_bits(addr));
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amdgpu_ring_write(ring, lower_32_bits(seq));
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