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arm64: dts: qcom: sm6350: Add DisplayPort controller

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Add the node for the DisplayPort controller found on the SM6350 SoC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240329-sm6350-dp-v2-3-e46dceb32ef5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Luca Weiss 2024-03-29 08:45:56 +01:00 committed by Bjorn Andersson
parent ac6d35b9b7
commit 62f87a3cac
1 changed files with 88 additions and 0 deletions
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88
arch/arm64/boot/dts/qcom/sm6350.dtsi
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@ -2064,6 +2064,14 @@ dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>; remote-endpoint = <&mdss_dsi0_in>;
}; };
}; };
port@2 {
reg = <2>;
dpu_intf0_out: endpoint {
remote-endpoint = <&mdss_dp_in>;
};
};
}; };
mdp_opp_table: opp-table { mdp_opp_table: opp-table {
@ -2101,6 +2109,86 @@ opp-560000000 {
}; };
}; };
mdss_dp: displayport-controller@ae90000 {
compatible = "qcom,sm6350-dp", "qcom,sm8350-dp";
reg = <0 0xae90000 0 0x200>,
<0 0xae90200 0 0x200>,
<0 0xae90400 0 0x600>,
<0 0xae91000 0 0x400>,
<0 0xae91400 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <12>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SM6350_CX>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dp_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
mdss_dp_out: endpoint {
};
};
};
dp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss_dsi0: dsi@ae94000 { mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>; reg = <0 0x0ae94000 0 0x400>;