mirror of
https://github.com/torvalds/linux.git
synced 2026-06-04 12:35:52 +02:00
memory: tegra: Updates for v6.17-rc1
Enable support for the memory and external memory controllers found on Tegra264. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmhxiZwACgkQ3SOs138+ s6GwjA//WLLmpGF1BVk2o4tiREwMttyQ8FW5aJF0XUl2CP6H1D+aekbrSZaQ0TIU vDxmtXZwaud8TWQ1OAsc2jVCzwEsowChQ8EO6+AcKejUlJNeFmJ+qm1OqP9OxzJY 9InZeTzYexsqxR4y9XPGAd6MWwCBlIrCzjfOZSRwEULCFlvzdZ1qFUbXBKboMMT7 Az2BFWiH8ecjlVAx0Ejy4rhrVTcGNznPDkPutUgQmWbamdET51h2/4tvUlNpM6jU Zpmj7rfma8u318RRz0gcGXMHNg8w8JGUM8TPl9hYrl9Y1hd56EKENxUf+uOw5i8M 6iE7gYuglhfXQ9FVjMkoE5ISecLQpGnT5nNC6mmSoG4KTFGhwoo2AMBGf4MLlm1O uE3F9+HTZzn0eZA6ney1EKcqpaf+MqdRVAduxYNXZpZN+Fe2QbwQ8ztRyAt3kOKL XRmuofsS7fe9TLWB6uRCabA84UbGvQlnn9CwBaCqtaGcYHWojO942PPO6Rg0nRaM V2WjmcIexXiiIp80xPQTp/+onj+STE+K/R0QzDjvImZQyXvUxBX8SY6TTAvO3gZm EoVbdDQc+9KhmQnUmlSg4WVdD21NmlfM6goloHA3EJVOyjyrehIzjLVrVppu3dy4 LEA6xl1Jy5xkufFdeF8jLugtkoPLYY0PM5cXJLgooakayujEru4= =4VeH -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmh/+DQACgkQmmx57+YA GNmgmg/+MEcHxmHS+Eh394bl8dqHlqSBKIG5rijCZduUKYJUcws68B0+IeW2Gswd s3Wk9y8O3lb8yACxDXdW9+Lt4AZEvUtM9ZFU2Wb09H0P83aqdNBWHWkwBrMuMlMH Bg7OGA5SLjJ3ke1RJQ00ba6dMKhfhxAUkRFeySzqMq843hRGObIZFAp6BpADJf31 7UjSz+yePlA5ZdzCeUssDyZvRRVQdUj1Hg2+nJE8g5MGZK04yoFz4hWPxXLb2PEw vcbQ4n7WZb3/MD2qdASAXk81vKYala8MHCdvBFALva5a1JjlY2h0JK/2jrcylx2W RgbBXThAiOSJ46KipO1qn1jSoyS8SQre8OKCiLRSdg73xoE5on8wRnLul4SbIGyo fzgC993YS2wCe3UUuhoa+Nm5dI630t0xdSFDeUEfAurDiNcLjsvOv0atHW572/fi ZPifQW0Rd69zPG/dXJxBFuXJjrcXW2XXJiDuXq/YTxFmMiWqHXu0XvxwH346gY9V P77MjSa2EJ1C8ZTTph5WOzkf2tO7gMKBL8shmHXz4DO/F81khKu6CIl275+JiEzn nDz4e9bcFAbvsnb39ItdA1vTdpP0SiQ05VRVrRER1gBl+1EvJ/QMIuQi8Izky8DB N3fiyuzxRhDaApXGRTWp/rrF6GEulzI7LEN9bCm6an/egYePQWQ= =oTmk -----END PGP SIGNATURE----- Merge tag 'tegra-for-6.17-memory' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers memory: tegra: Updates for v6.17-rc1 Enable support for the memory and external memory controllers found on Tegra264. * tag 'tegra-for-6.17-memory' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Add Tegra264 MC and EMC support dt-bindings: memory: tegra: Add Tegra264 support Link: https://lore.kernel.org/r/20250711220943.2389322-4-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
62bd59ca1c
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@ -32,6 +32,7 @@ properties:
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- nvidia,tegra186-mc
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- nvidia,tegra194-mc
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- nvidia,tegra234-mc
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- nvidia,tegra264-mc
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reg:
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minItems: 6
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@ -42,8 +43,12 @@ properties:
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maxItems: 18
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interrupts:
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items:
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- description: MC general interrupt
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minItems: 1
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maxItems: 8
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interrupt-names:
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minItems: 1
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maxItems: 8
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"#address-cells":
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const: 2
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@ -74,6 +79,7 @@ patternProperties:
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- nvidia,tegra186-emc
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- nvidia,tegra194-emc
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- nvidia,tegra234-emc
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- nvidia,tegra264-emc
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reg:
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minItems: 1
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@ -127,6 +133,15 @@ patternProperties:
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reg:
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minItems: 2
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- if:
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properties:
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compatible:
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const: nvidia,tegra264-emc
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then:
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properties:
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reg:
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minItems: 2
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additionalProperties: false
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required:
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@ -158,6 +173,12 @@ allOf:
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- const: ch2
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- const: ch3
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interrupts:
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items:
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- description: MC general interrupt
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interrupt-names: false
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- if:
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properties:
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compatible:
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@ -189,6 +210,12 @@ allOf:
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- const: ch14
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- const: ch15
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interrupts:
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items:
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- description: MC general interrupt
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interrupt-names: false
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- if:
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properties:
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compatible:
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@ -220,6 +247,59 @@ allOf:
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- const: ch14
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- const: ch15
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interrupts:
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items:
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- description: MC general interrupt
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interrupt-names: false
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- if:
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properties:
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compatible:
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const: nvidia,tegra264-mc
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then:
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properties:
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reg:
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minItems: 17
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maxItems: 17
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description: 17 memory controller channels
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reg-names:
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items:
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- const: broadcast
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- const: ch0
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- const: ch1
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- const: ch2
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- const: ch3
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- const: ch4
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- const: ch5
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- const: ch6
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- const: ch7
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- const: ch8
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- const: ch9
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- const: ch10
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- const: ch11
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- const: ch12
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- const: ch13
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- const: ch14
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- const: ch15
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interrupts:
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minItems: 8
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maxItems: 8
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description: One interrupt line for each MC component
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interrupt-names:
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items:
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- const: mcf
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- const: hub1
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- const: hub2
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- const: hub3
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- const: hub4
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- const: hub5
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- const: sbs
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- const: channel
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additionalProperties: false
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required:
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@ -10,6 +10,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186.o tegra234.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra186.o tegra264.o
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obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
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@ -21,5 +22,6 @@ obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
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obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o
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obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o
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obj-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186-emc.o
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obj-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra186-emc.o
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tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clk.h>
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@ -48,6 +48,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
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#endif
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#ifdef CONFIG_ARCH_TEGRA_234_SOC
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{ .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_264_SOC
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{ .compatible = "nvidia,tegra264-mc", .data = &tegra264_mc_soc },
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#endif
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{ /* sentinel */ }
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};
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef MEMORY_TEGRA_MC_H
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@ -182,6 +182,10 @@ extern const struct tegra_mc_soc tegra194_mc_soc;
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extern const struct tegra_mc_soc tegra234_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_264_SOC
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extern const struct tegra_mc_soc tegra264_mc_soc;
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#endif
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#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
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defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
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@ -193,7 +197,8 @@ extern const struct tegra_mc_ops tegra30_mc_ops;
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#if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
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defined(CONFIG_ARCH_TEGRA_194_SOC) || \
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defined(CONFIG_ARCH_TEGRA_234_SOC)
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defined(CONFIG_ARCH_TEGRA_234_SOC) || \
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defined(CONFIG_ARCH_TEGRA_264_SOC)
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extern const struct tegra_mc_ops tegra186_mc_ops;
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#endif
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2019 NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2019-2025 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clk.h>
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@ -393,6 +393,9 @@ static const struct of_device_id tegra186_emc_of_match[] = {
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#endif
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#if defined(CONFIG_ARCH_TEGRA_234_SOC)
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{ .compatible = "nvidia,tegra234-emc" },
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#endif
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#if defined(CONFIG_ARCH_TEGRA_264_SOC)
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{ .compatible = "nvidia,tegra264-emc" },
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#endif
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{ /* sentinel */ }
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};
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2017-2025 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/io.h>
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@ -26,11 +26,24 @@
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static int tegra186_mc_probe(struct tegra_mc *mc)
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{
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struct platform_device *pdev = to_platform_device(mc->dev);
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struct resource *res;
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unsigned int i;
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char name[8];
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int err;
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mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
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/*
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* From Tegra264, the SID region is not present in MC node and BROADCAST is first.
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* The common function 'tegra_mc_probe()' already maps first region entry from DT.
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* Check if the SID region is present in DT then map BROADCAST. Otherwise, consider
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* the first entry mapped in mc probe as the BROADCAST region. This is done to avoid
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* mapping the region twice when SID is not present and keep backward compatibility.
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*/
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid");
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if (res)
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mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
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else
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mc->bcast_ch_regs = mc->regs;
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if (IS_ERR(mc->bcast_ch_regs)) {
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if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
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dev_warn(&pdev->dev,
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50
drivers/memory/tegra/tegra264-bwmgr.h
Normal file
50
drivers/memory/tegra/tegra264-bwmgr.h
Normal file
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@ -0,0 +1,50 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (C) 2025 NVIDIA CORPORATION. All rights reserved. */
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#ifndef MEMORY_TEGRA_TEGRA264_BWMGR_H
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#define MEMORY_TEGRA_TEGRA264_BWMGR_H
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#define TEGRA264_BWMGR_ICC_PRIMARY 1
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#define TEGRA264_BWMGR_DEBUG 2
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#define TEGRA264_BWMGR_CPU_CLUSTER0 3
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#define TEGRA264_BWMGR_CPU_CLUSTER1 4
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#define TEGRA264_BWMGR_CPU_CLUSTER2 5
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#define TEGRA264_BWMGR_CPU_CLUSTER3 6
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#define TEGRA264_BWMGR_CPU_CLUSTER4 7
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#define TEGRA264_BWMGR_CPU_CLUSTER5 8
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#define TEGRA264_BWMGR_CPU_CLUSTER6 9
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#define TEGRA264_BWMGR_CACTMON 10
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#define TEGRA264_BWMGR_DISPLAY 11
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#define TEGRA264_BWMGR_VI 12
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#define TEGRA264_BWMGR_APE 13
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#define TEGRA264_BWMGR_VIFAL 14
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#define TEGRA264_BWMGR_GPU 15
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#define TEGRA264_BWMGR_EQOS 16
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#define TEGRA264_BWMGR_PCIE_0 17
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#define TEGRA264_BWMGR_PCIE_1 18
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#define TEGRA264_BWMGR_PCIE_2 19
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#define TEGRA264_BWMGR_PCIE_3 20
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#define TEGRA264_BWMGR_PCIE_4 21
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#define TEGRA264_BWMGR_PCIE_5 22
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#define TEGRA264_BWMGR_SDMMC_1 23
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#define TEGRA264_BWMGR_SDMMC_2 24
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#define TEGRA264_BWMGR_NVDEC 25
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#define TEGRA264_BWMGR_NVENC 26
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#define TEGRA264_BWMGR_NVJPG_0 27
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#define TEGRA264_BWMGR_NVJPG_1 28
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#define TEGRA264_BWMGR_OFAA 29
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#define TEGRA264_BWMGR_XUSB_HOST 30
|
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#define TEGRA264_BWMGR_XUSB_DEV 31
|
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#define TEGRA264_BWMGR_TSEC 32
|
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#define TEGRA264_BWMGR_VIC 33
|
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#define TEGRA264_BWMGR_APEDMA 34
|
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#define TEGRA264_BWMGR_SE 35
|
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#define TEGRA264_BWMGR_ISP 36
|
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#define TEGRA264_BWMGR_HDA 37
|
||||
#define TEGRA264_BWMGR_VI2FAL 38
|
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#define TEGRA264_BWMGR_VI2 39
|
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#define TEGRA264_BWMGR_RCE 40
|
||||
#define TEGRA264_BWMGR_PVA 41
|
||||
#define TEGRA264_BWMGR_NVPMODEL 42
|
||||
|
||||
#endif
|
||||
313
drivers/memory/tegra/tegra264.c
Normal file
313
drivers/memory/tegra/tegra264.c
Normal file
|
|
@ -0,0 +1,313 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/memory/nvidia,tegra264.h>
|
||||
|
||||
#include <linux/interconnect.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/tegra-icc.h>
|
||||
|
||||
#include <soc/tegra/bpmp.h>
|
||||
#include <soc/tegra/mc.h>
|
||||
|
||||
#include "mc.h"
|
||||
#include "tegra264-bwmgr.h"
|
||||
|
||||
/*
|
||||
* MC Client entries are sorted in the increasing order of the
|
||||
* override and security register offsets.
|
||||
*/
|
||||
static const struct tegra_mc_client tegra264_mc_clients[] = {
|
||||
{
|
||||
.id = TEGRA264_MEMORY_CLIENT_HDAR,
|
||||
.name = "hdar",
|
||||
.bpmp_id = TEGRA264_BWMGR_HDA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HDAW,
|
||||
.name = "hdaw",
|
||||
.bpmp_id = TEGRA264_BWMGR_HDA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE0R,
|
||||
.name = "mgbe0r",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE0W,
|
||||
.name = "mgbe0w",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE1R,
|
||||
.name = "mgbe1r",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE1W,
|
||||
.name = "mgbe1w",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SDMMC0R,
|
||||
.name = "sdmmc0r",
|
||||
.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SDMMC0W,
|
||||
.name = "sdmmc0w",
|
||||
.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VICR,
|
||||
.name = "vicr",
|
||||
.bpmp_id = TEGRA264_BWMGR_VIC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VICW,
|
||||
.name = "vicw",
|
||||
.bpmp_id = TEGRA264_BWMGR_VIC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_APER,
|
||||
.name = "aper",
|
||||
.bpmp_id = TEGRA264_BWMGR_APE,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_APEW,
|
||||
.name = "apew",
|
||||
.bpmp_id = TEGRA264_BWMGR_APE,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_APEDMAR,
|
||||
.name = "apedmar",
|
||||
.bpmp_id = TEGRA264_BWMGR_APEDMA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_APEDMAW,
|
||||
.name = "apedmaw",
|
||||
.bpmp_id = TEGRA264_BWMGR_APEDMA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VIFALCONR,
|
||||
.name = "vifalconr",
|
||||
.bpmp_id = TEGRA264_BWMGR_VIFAL,
|
||||
.type = TEGRA_ICC_ISO_VIFAL,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VIFALCONW,
|
||||
.name = "vifalconw",
|
||||
.bpmp_id = TEGRA264_BWMGR_VIFAL,
|
||||
.type = TEGRA_ICC_ISO_VIFAL,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_RCER,
|
||||
.name = "rcer",
|
||||
.bpmp_id = TEGRA264_BWMGR_RCE,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_RCEW,
|
||||
.name = "rcew",
|
||||
.bpmp_id = TEGRA264_BWMGR_RCE,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE0W,
|
||||
.name = "pcie0w",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_0,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE1R,
|
||||
.name = "pcie1r",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE1W,
|
||||
.name = "pcie1w",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE2AR,
|
||||
.name = "pcie2ar",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_2,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE2AW,
|
||||
.name = "pcie2aw",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_2,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE3R,
|
||||
.name = "pcie3r",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_3,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE3W,
|
||||
.name = "pcie3w",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_3,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE4R,
|
||||
.name = "pcie4r",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_4,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE4W,
|
||||
.name = "pcie4w",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_4,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE5R,
|
||||
.name = "pcie5r",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_5,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE5W,
|
||||
.name = "pcie5w",
|
||||
.bpmp_id = TEGRA264_BWMGR_PCIE_5,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_GPUR02MC,
|
||||
.name = "gpur02mc",
|
||||
.bpmp_id = TEGRA264_BWMGR_GPU,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_GPUW02MC,
|
||||
.name = "gpuw02mc",
|
||||
.bpmp_id = TEGRA264_BWMGR_GPU,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_NVDECSRD2MC,
|
||||
.name = "nvdecsrd2mc",
|
||||
.bpmp_id = TEGRA264_BWMGR_NVDEC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_NVDECSWR2MC,
|
||||
.name = "nvdecswr2mc",
|
||||
.bpmp_id = TEGRA264_BWMGR_NVDEC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* tegra264_mc_icc_set() - Pass MC client info to the BPMP-FW
|
||||
* @src: ICC node for Memory Controller's (MC) Client
|
||||
* @dst: ICC node for Memory Controller (MC)
|
||||
*
|
||||
* Passing the current request info from the MC to the BPMP-FW where
|
||||
* LA and PTSA registers are accessed and the final EMC freq is set
|
||||
* based on client_id, type, latency and bandwidth.
|
||||
* icc_set_bw() makes set_bw calls for both MC and EMC providers in
|
||||
* sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'.
|
||||
* So, the data passed won't be updated by concurrent set calls from
|
||||
* other clients.
|
||||
*/
|
||||
static int tegra264_mc_icc_set(struct icc_node *src, struct icc_node *dst)
|
||||
{
|
||||
struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider);
|
||||
struct mrq_bwmgr_int_request bwmgr_req = { 0 };
|
||||
struct mrq_bwmgr_int_response bwmgr_resp = { 0 };
|
||||
const struct tegra_mc_client *pclient = src->data;
|
||||
struct tegra_bpmp_message msg;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Same Src and Dst node will happen during boot from icc_node_add().
|
||||
* This can be used to pre-initialize and set bandwidth for all clients
|
||||
* before their drivers are loaded. We are skipping this case as for us,
|
||||
* the pre-initialization already happened in Bootloader(MB2) and BPMP-FW.
|
||||
*/
|
||||
if (src->id == dst->id)
|
||||
return 0;
|
||||
|
||||
if (!mc->bwmgr_mrq_supported)
|
||||
return 0;
|
||||
|
||||
if (!mc->bpmp) {
|
||||
dev_err(mc->dev, "BPMP reference NULL\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
if (pclient->type == TEGRA_ICC_NISO)
|
||||
bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
|
||||
else
|
||||
bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw;
|
||||
|
||||
bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id;
|
||||
|
||||
bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET;
|
||||
bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw;
|
||||
bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS;
|
||||
|
||||
memset(&msg, 0, sizeof(msg));
|
||||
msg.mrq = MRQ_BWMGR_INT;
|
||||
msg.tx.data = &bwmgr_req;
|
||||
msg.tx.size = sizeof(bwmgr_req);
|
||||
msg.rx.data = &bwmgr_resp;
|
||||
msg.rx.size = sizeof(bwmgr_resp);
|
||||
|
||||
ret = tegra_bpmp_transfer(mc->bpmp, &msg);
|
||||
if (ret < 0) {
|
||||
dev_err(mc->dev, "BPMP transfer failed: %d\n", ret);
|
||||
goto error;
|
||||
}
|
||||
if (msg.rx.ret < 0) {
|
||||
pr_err("failed to set bandwidth for %u: %d\n",
|
||||
bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
error:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra264_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
|
||||
{
|
||||
struct icc_provider *p = node->provider;
|
||||
struct tegra_mc *mc = icc_provider_to_tegra_mc(p);
|
||||
|
||||
if (!mc->bwmgr_mrq_supported)
|
||||
return 0;
|
||||
|
||||
*agg_avg += avg_bw;
|
||||
*agg_peak = max(*agg_peak, peak_bw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra264_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
|
||||
{
|
||||
*avg = 0;
|
||||
*peak = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct tegra_mc_icc_ops tegra264_mc_icc_ops = {
|
||||
.xlate = tegra_mc_icc_xlate,
|
||||
.aggregate = tegra264_mc_icc_aggregate,
|
||||
.get_bw = tegra264_mc_icc_get_init_bw,
|
||||
.set = tegra264_mc_icc_set,
|
||||
};
|
||||
|
||||
const struct tegra_mc_soc tegra264_mc_soc = {
|
||||
.num_clients = ARRAY_SIZE(tegra264_mc_clients),
|
||||
.clients = tegra264_mc_clients,
|
||||
.num_address_bits = 40,
|
||||
.num_channels = 16,
|
||||
.client_id_mask = 0x1ff,
|
||||
.intmask = MC_INT_DECERR_ROUTE_SANITY |
|
||||
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
|
||||
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
|
||||
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
|
||||
.has_addr_hi_reg = true,
|
||||
.ops = &tegra186_mc_ops,
|
||||
.icc_ops = &tegra264_mc_icc_ops,
|
||||
.ch_intmask = 0x0000ff00,
|
||||
.global_intstatus_channel_shift = 8,
|
||||
/*
|
||||
* Additionally, there are lite carveouts but those are not currently
|
||||
* supported.
|
||||
*/
|
||||
.num_carveouts = 32,
|
||||
};
|
||||
136
include/dt-bindings/memory/nvidia,tegra264.h
Normal file
136
include/dt-bindings/memory/nvidia,tegra264.h
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */
|
||||
|
||||
#ifndef DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H
|
||||
#define DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H
|
||||
|
||||
#define TEGRA264_SID(x) ((x) << 8)
|
||||
|
||||
/*
|
||||
* SMMU stream IDs
|
||||
*/
|
||||
|
||||
#define TEGRA264_SID_AON TEGRA264_SID(0x01)
|
||||
#define TEGRA264_SID_APE TEGRA264_SID(0x02)
|
||||
#define TEGRA264_SID_ETR TEGRA264_SID(0x03)
|
||||
#define TEGRA264_SID_BPMP TEGRA264_SID(0x04)
|
||||
#define TEGRA264_SID_DCE TEGRA264_SID(0x05)
|
||||
#define TEGRA264_SID_EQOS TEGRA264_SID(0x06)
|
||||
#define TEGRA264_SID_GPCDMA TEGRA264_SID(0x08)
|
||||
#define TEGRA264_SID_DISP TEGRA264_SID(0x09)
|
||||
#define TEGRA264_SID_HDA TEGRA264_SID(0x0a)
|
||||
#define TEGRA264_SID_HOST1X TEGRA264_SID(0x0b)
|
||||
#define TEGRA264_SID_ISP0 TEGRA264_SID(0x0c)
|
||||
#define TEGRA264_SID_ISP1 TEGRA264_SID(0x0d)
|
||||
#define TEGRA264_SID_PMA0 TEGRA264_SID(0x0e)
|
||||
#define TEGRA264_SID_FSI0 TEGRA264_SID(0x0f)
|
||||
#define TEGRA264_SID_FSI1 TEGRA264_SID(0x10)
|
||||
#define TEGRA264_SID_PVA TEGRA264_SID(0x11)
|
||||
#define TEGRA264_SID_SDMMC0 TEGRA264_SID(0x12)
|
||||
#define TEGRA264_SID_MGBE0 TEGRA264_SID(0x13)
|
||||
#define TEGRA264_SID_MGBE1 TEGRA264_SID(0x14)
|
||||
#define TEGRA264_SID_MGBE2 TEGRA264_SID(0x15)
|
||||
#define TEGRA264_SID_MGBE3 TEGRA264_SID(0x16)
|
||||
#define TEGRA264_SID_MSSSEQ TEGRA264_SID(0x17)
|
||||
#define TEGRA264_SID_SE TEGRA264_SID(0x18)
|
||||
#define TEGRA264_SID_SEU1 TEGRA264_SID(0x19)
|
||||
#define TEGRA264_SID_SEU2 TEGRA264_SID(0x1a)
|
||||
#define TEGRA264_SID_SEU3 TEGRA264_SID(0x1b)
|
||||
#define TEGRA264_SID_PSC TEGRA264_SID(0x1c)
|
||||
#define TEGRA264_SID_OESP TEGRA264_SID(0x23)
|
||||
#define TEGRA264_SID_SB TEGRA264_SID(0x24)
|
||||
#define TEGRA264_SID_XSPI0 TEGRA264_SID(0x25)
|
||||
#define TEGRA264_SID_TSEC TEGRA264_SID(0x29)
|
||||
#define TEGRA264_SID_UFS TEGRA264_SID(0x2a)
|
||||
#define TEGRA264_SID_RCE TEGRA264_SID(0x2b)
|
||||
#define TEGRA264_SID_RCE1 TEGRA264_SID(0x2c)
|
||||
#define TEGRA264_SID_VI TEGRA264_SID(0x2e)
|
||||
#define TEGRA264_SID_VI1 TEGRA264_SID(0x2f)
|
||||
#define TEGRA264_SID_VIC TEGRA264_SID(0x30)
|
||||
#define TEGRA264_SID_XUSB_DEV TEGRA264_SID(0x32)
|
||||
#define TEGRA264_SID_XUSB_DEV1 TEGRA264_SID(0x33)
|
||||
#define TEGRA264_SID_XUSB_DEV2 TEGRA264_SID(0x34)
|
||||
#define TEGRA264_SID_XUSB_DEV3 TEGRA264_SID(0x35)
|
||||
#define TEGRA264_SID_XUSB_DEV4 TEGRA264_SID(0x36)
|
||||
#define TEGRA264_SID_XUSB_DEV5 TEGRA264_SID(0x37)
|
||||
|
||||
/*
|
||||
* memory client IDs
|
||||
*/
|
||||
|
||||
/* HOST1X read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_HOST1XR 0x16
|
||||
/* VIC read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VICR 0x6c
|
||||
/* VIC Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VICW 0x6d
|
||||
/* VI R5 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VIW 0x72
|
||||
#define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC 0x78
|
||||
#define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC 0x79
|
||||
/* Audio processor(APE) Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APER 0x7a
|
||||
/* Audio processor(APE) Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APEW 0x7b
|
||||
/* Audio DMA Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APEDMAR 0x9f
|
||||
/* Audio DMA Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APEDMAW 0xa0
|
||||
#define TEGRA264_MEMORY_CLIENT_GPUR02MC 0xb6
|
||||
#define TEGRA264_MEMORY_CLIENT_GPUW02MC 0xb7
|
||||
/* VI Falcon Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VIFALCONR 0xbc
|
||||
/* VI Falcon Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VIFALCONW 0xbd
|
||||
/* Read Client of RCE */
|
||||
#define TEGRA264_MEMORY_CLIENT_RCER 0xd2
|
||||
/* Write client of RCE */
|
||||
#define TEGRA264_MEMORY_CLIENT_RCEW 0xd3
|
||||
/* PCIE0/MSI Write clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE0W 0xd9
|
||||
/* PCIE1/RPX4 Read clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE1R 0xda
|
||||
/* PCIE1/RPX4 Write clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE1W 0xdb
|
||||
/* PCIE2/DMX4 Read clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE2AR 0xdc
|
||||
/* PCIE2/DMX4 Write clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE2AW 0xdd
|
||||
/* PCIE3/RPX4 Read clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE3R 0xde
|
||||
/* PCIE3/RPX4 Write clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE3W 0xdf
|
||||
/* PCIE4/DMX8 Read clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE4R 0xe0
|
||||
/* PCIE4/DMX8 Write clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE4W 0xe1
|
||||
/* PCIE5/DMX4 Read clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2
|
||||
/* PCIE5/DMX4 Write clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3
|
||||
/* UFS Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_UFSR 0x15c
|
||||
/* UFS write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_UFSW 0x15d
|
||||
/* HDA Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_HDAR 0x17c
|
||||
/* HDA Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_HDAW 0x17d
|
||||
/* Disp ISO Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_DISPR 0x182
|
||||
/* MGBE0 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_MGBE0R 0x1a2
|
||||
/* MGBE0 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_MGBE0W 0x1a3
|
||||
/* MGBE1 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_MGBE1R 0x1a4
|
||||
/* MGBE1 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_MGBE1W 0x1a5
|
||||
/* VI1 R5 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VI1W 0x1a6
|
||||
/* SDMMC0 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_SDMMC0R 0x1c2
|
||||
/* SDMMC0 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_SDMMC0W 0x1c3
|
||||
|
||||
#endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */
|
||||
Loading…
Reference in New Issue
Block a user