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RISC-V SpacemiT clock changes for 6.20

Browse Source 
- Fix driver to build as module
 - Refactor to extract common code
 - Add clock support for new K3 SoC
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQKvBAABCgCZFiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmlm4qAbFIAAAAAABAAO
 bWFudTIsMi41KzEuMTEsMiwyXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25z
 Lm9wZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCNUJBQjhDOUMzMUI3MTE1NjcwMjIz
 REMzMUFBRUE0NzU5NERCQkVEAAoJEDGq6kdZTbvtxYMQAIFTA5m2VLZkHKxASn/f
 t/GLhWvw9O7g4wlyaC9DoALRCl241P9UF+tjLNDP1MqzZ2jsQ1dyXuVVn4VnHBty
 rLhjpUcZPccsHPLt+T5vkFPDqKydaEAJwSTJmdbkTHc0ipr3OmSeMMphrduF9J0C
 WwbqMYC456DJzMLlTYSasaFH6tZacxcFgFsDz0TXePu+ctHbRCjMNLf84dBU4egm
 KbgoRQs+rejm+zO6pNK/ZuF0o3AnU/qLmIPGp61khwyEobX9eF9QgaSgcXvEJwsv
 BePWZPIGbKUWEvb/5HKHMD3bVC31m6KqCeIpVTNqJ0WCNl0cepAPJhddEikrI3zA
 v3SHWpptGSrxOAK4EumqVVFe3h9NgNDCYmMTiRHLpig6y3uS6MHzk1jLJYKXHq+u
 tz32RZ75FqVuG9aU8ZAcECzWrATRAQfrwAl5iX6bKq3VjkeOH2OUFRq3FjnhXeQm
 I3MsuIdz46w/+AlixEfSgU/+peAJ/O/oOF/LcpioOj3Xhy6m0g1ahGbbUveflq/+
 MNF2Q4q/PRmswgp6o2Q//0MB0fQA85deMz3BmtJ3dRJrWkOB3VNcq9zZyQl9zc23
 5AyTwdH6BapkTT8H1Gu8aIxDg3jbJQBdQNarW76bWm74U0KqlcpDm/2dd6Vvax71
 vjZy57ZsH3w3MOlYKWQOfG9B
 =F1by
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmlxI4EUHHN3Ym95ZEBj
 aHJvbWl1bS5vcmcACgkQrQKIl8bklSWExQ//SXS1w4qVsTER8FPoVYhiVBFggHMV
 WAWYjjWsN73iPO/bL090VOTGFpirm5wwDWe2y1nVMtEUgmqI4uqZ8hIBr4+Qp7sS
 8TXUhw1PhMy8sb9LSAOy1uYfgkdYqH0ka/RT7dvYxASHytMiI6KM80sePX3mJ5rp
 7d3GiW0mWDX+UBM0LDkMwBQ4rvrLOdCtzS5krILGopooRLp/OzVcW51UvqEgFYHO
 A9QS0tBrge2g2QJHY1prhq/pNcZdeySGPYEiw7U2QeLZrz9si4mK96PjyEZ21UX9
 II4mqW1KFDLFdyqBK0iMCN2mUAm/JzVZIyT2Nud72AWmwQap5tSWQR1jWse/YWsc
 2WIHXntrd/OTWprgNHHIta85yw2HzCu2ES85LjrpIroyghULkXExGiHc3ey1BHYJ
 72TPBnnlKNilGNutpdfCRYoCYgSS97HIfvAJAfwv1uom9GiRfdOCVMH7uaiq7q0G
 6wG8PduJ7W2PBbvTSCa6Y4n4UbpDaSUKtWbITw2h/3tXDt4Y7oDsaNTQptzubXHM
 DZ6zB4vBOSebb+hs0iLyRVJSCY6Xtl/t/6SvwxULfI3OkBmg1dsM2lXPkuYb9YVc
 Go4dz9EWPfBE/oV/J/Fv0ucyneaw0BupdKp31axN22APEM+l00gq6byDcw3ji8l2
 XSHjyqsbX6gx71M=
 =3ZRo
 -----END PGP SIGNATURE-----

Merge tag 'spacemit-clk-for-6.20-1' of https://github.com/spacemit-com/linux into clk-spacemit

Pull SpacemiT clock driver updates from Yixun Lan:

 - Allow SpacemiT driver to be built as module
 - Refactor SpacemiT driver to extract common code
 - Add support for SpacemiT K3 SoC clk hardware

* tag 'spacemit-clk-for-6.20-1' of https://github.com/spacemit-com/linux:
  clk: spacemit: k3: add the clock tree
  clk: spacemit: k3: extract common header
  clk: spacemit: ccu_pll: add plla type clock
  clk: spacemit: ccu_mix: add inverted enable gate clock
  dt-bindings: soc: spacemit: k3: add clock support
  clk: spacemit: add platform SoC prefix to reset name
  clk: spacemit: extract common ccu functions
  reset: spacemit: fix auxiliary device id
  clk: spacemit: prepare common ccu header
  clk: spacemit: Hide common clock driver from user controller
  clk: spacemit: Respect Kconfig setting when building modules
This commit is contained in:
Stephen Boyd 2026-01-21 11:04:31 -08:00
commit 6294bb8eda
18 changed files with 2609 additions and 221 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml
View File

@ -4,14 +4,16 @@
$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT K1 PLL
title: SpacemiT K1/K3 PLL
maintainers:
- Haylen Chu <heylenay@4d2.org>
properties:
compatible:
const: spacemit,k1-pll
enum:
- spacemit,k1-pll
- spacemit,k3-pll
reg:
maxItems: 1
@ -28,7 +30,8 @@ properties:
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K1 SoC, check <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K3 SoC, check <dt-bindings/clock/spacemit,k3-clocks.h> for valid indices.
required:
- compatible

14
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
View File

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT K1 SoC System Controller
title: SpacemiT K1/K3 SoC System Controller
maintainers:
- Haylen Chu <heylenay@4d2.org>
@ -22,6 +22,10 @@ properties:
- spacemit,k1-syscon-rcpu
- spacemit,k1-syscon-rcpu2
- spacemit,k1-syscon-apbc2
- spacemit,k3-syscon-apbc
- spacemit,k3-syscon-apmu
- spacemit,k3-syscon-dciu
- spacemit,k3-syscon-mpmu
reg:
maxItems: 1
@ -39,7 +43,8 @@ properties:
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K1 SoC, check <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K3 SoC, check <dt-bindings/clock/spacemit,k3-clocks.h> for valid indices.
"#power-domain-cells":
const: 1
@ -60,6 +65,8 @@ allOf:
enum:
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
- spacemit,k3-syscon-apmu
- spacemit,k3-syscon-mpmu
then:
required:
- "#power-domain-cells"
@ -74,6 +81,9 @@ allOf:
- spacemit,k1-syscon-apbc
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
- spacemit,k3-syscon-apbc
- spacemit,k3-syscon-apmu
- spacemit,k3-syscon-mpmu
then:
required:
- clocks

20
drivers/clk/spacemit/Kconfig
View File

@ -1,19 +1,23 @@
# SPDX-License-Identifier: GPL-2.0-only
config SPACEMIT_CCU
tristate "Clock support for SpacemiT SoCs"
menu "Clock support for SpacemiT platforms"
depends on ARCH_SPACEMIT || COMPILE_TEST
config SPACEMIT_CCU
tristate
select AUXILIARY_BUS
select MFD_SYSCON
help
Say Y to enable clock controller unit support for SpacemiT SoCs.
if SPACEMIT_CCU
config SPACEMIT_K1_CCU
tristate "Support for SpacemiT K1 SoC"
depends on ARCH_SPACEMIT || COMPILE_TEST
select SPACEMIT_CCU
help
Support for clock controller unit in SpacemiT K1 SoC.
endif
config SPACEMIT_K3_CCU
tristate "Support for SpacemiT K3 SoC"
select SPACEMIT_CCU
help
Support for clock controller unit in SpacemiT K3 SoC.
endmenu

12
drivers/clk/spacemit/Makefile
View File

@ -1,5 +1,13 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_SPACEMIT_K1_CCU) = spacemit-ccu-k1.o
spacemit-ccu-k1-y = ccu_pll.o ccu_mix.o ccu_ddn.o
obj-$(CONFIG_SPACEMIT_CCU) += spacemit-ccu.o
spacemit-ccu-y += ccu_common.o
spacemit-ccu-y += ccu_pll.o
spacemit-ccu-y += ccu_mix.o
spacemit-ccu-y += ccu_ddn.o
obj-$(CONFIG_SPACEMIT_K1_CCU) += spacemit-ccu-k1.o
spacemit-ccu-k1-y += ccu-k1.o
obj-$(CONFIG_SPACEMIT_K3_CCU) += spacemit-ccu-k3.o
spacemit-ccu-k3-y += ccu-k3.o

192
drivers/clk/spacemit/ccu-k1.c
View File

@ -5,15 +5,10 @@
*/
#include <linux/array_size.h>
#include <linux/auxiliary_bus.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/idr.h>
#include <linux/mfd/syscon.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <soc/spacemit/k1-syscon.h>
#include "ccu_common.h"
@ -23,14 +18,6 @@
#include <dt-bindings/clock/spacemit,k1-syscon.h>
struct spacemit_ccu_data {
const char *reset_name;
struct clk_hw **hws;
size_t num;
};
static DEFINE_IDA(auxiliary_ids);
/* APBS clocks start, APBS region contains and only contains all PLL clocks */
/*
@ -802,7 +789,7 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_mpmu_data = {
.reset_name = "mpmu-reset",
.reset_name = "k1-mpmu-reset",
.hws = k1_ccu_mpmu_hws,
.num = ARRAY_SIZE(k1_ccu_mpmu_hws),
};
@ -913,7 +900,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_apbc_data = {
.reset_name = "apbc-reset",
.reset_name = "k1-apbc-reset",
.hws = k1_ccu_apbc_hws,
.num = ARRAY_SIZE(k1_ccu_apbc_hws),
};
@ -984,184 +971,23 @@ static struct clk_hw *k1_ccu_apmu_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_apmu_data = {
.reset_name = "apmu-reset",
.reset_name = "k1-apmu-reset",
.hws = k1_ccu_apmu_hws,
.num = ARRAY_SIZE(k1_ccu_apmu_hws),
};
static const struct spacemit_ccu_data k1_ccu_rcpu_data = {
.reset_name = "rcpu-reset",
.reset_name = "k1-rcpu-reset",
};
static const struct spacemit_ccu_data k1_ccu_rcpu2_data = {
.reset_name = "rcpu2-reset",
.reset_name = "k1-rcpu2-reset",
};
static const struct spacemit_ccu_data k1_ccu_apbc2_data = {
.reset_name = "apbc2-reset",
.reset_name = "k1-apbc2-reset",
};
static int spacemit_ccu_register(struct device *dev,
struct regmap *regmap,
struct regmap *lock_regmap,
const struct spacemit_ccu_data *data)
{
struct clk_hw_onecell_data *clk_data;
int i, ret;
/* Nothing to do if the CCU does not implement any clocks */
if (!data->hws)
return 0;
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
clk_data->num = data->num;
for (i = 0; i < data->num; i++) {
struct clk_hw *hw = data->hws[i];
struct ccu_common *common;
const char *name;
if (!hw) {
clk_data->hws[i] = ERR_PTR(-ENOENT);
continue;
}
name = hw->init->name;
common = hw_to_ccu_common(hw);
common->regmap = regmap;
common->lock_regmap = lock_regmap;
ret = devm_clk_hw_register(dev, hw);
if (ret) {
dev_err(dev, "Cannot register clock %d - %s\n",
i, name);
return ret;
}
clk_data->hws[i] = hw;
}
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
if (ret)
dev_err(dev, "failed to add clock hardware provider (%d)\n", ret);
return ret;
}
static void spacemit_cadev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
ida_free(&auxiliary_ids, adev->id);
kfree(to_spacemit_ccu_adev(adev));
}
static void spacemit_adev_unregister(void *data)
{
struct auxiliary_device *adev = data;
auxiliary_device_delete(adev);
auxiliary_device_uninit(adev);
}
static int spacemit_ccu_reset_register(struct device *dev,
struct regmap *regmap,
const char *reset_name)
{
struct spacemit_ccu_adev *cadev;
struct auxiliary_device *adev;
int ret;
/* Nothing to do if the CCU does not implement a reset controller */
if (!reset_name)
return 0;
cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
if (!cadev)
return -ENOMEM;
cadev->regmap = regmap;
adev = &cadev->adev;
adev->name = reset_name;
adev->dev.parent = dev;
adev->dev.release = spacemit_cadev_release;
adev->dev.of_node = dev->of_node;
ret = ida_alloc(&auxiliary_ids, GFP_KERNEL);
if (ret < 0)
goto err_free_cadev;
adev->id = ret;
ret = auxiliary_device_init(adev);
if (ret)
goto err_free_aux_id;
ret = auxiliary_device_add(adev);
if (ret) {
auxiliary_device_uninit(adev);
return ret;
}
return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev);
err_free_aux_id:
ida_free(&auxiliary_ids, adev->id);
err_free_cadev:
kfree(cadev);
return ret;
}
static int k1_ccu_probe(struct platform_device *pdev)
{
struct regmap *base_regmap, *lock_regmap = NULL;
const struct spacemit_ccu_data *data;
struct device *dev = &pdev->dev;
int ret;
base_regmap = device_node_to_regmap(dev->of_node);
if (IS_ERR(base_regmap))
return dev_err_probe(dev, PTR_ERR(base_regmap),
"failed to get regmap\n");
/*
* The lock status of PLLs locate in MPMU region, while PLLs themselves
* are in APBS region. Reference to MPMU syscon is required to check PLL
* status.
*/
if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) {
struct device_node *mpmu = of_parse_phandle(dev->of_node,
"spacemit,mpmu", 0);
if (!mpmu)
return dev_err_probe(dev, -ENODEV,
"Cannot parse MPMU region\n");
lock_regmap = device_node_to_regmap(mpmu);
of_node_put(mpmu);
if (IS_ERR(lock_regmap))
return dev_err_probe(dev, PTR_ERR(lock_regmap),
"failed to get lock regmap\n");
}
data = of_device_get_match_data(dev);
ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data);
if (ret)
return dev_err_probe(dev, ret, "failed to register clocks\n");
ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name);
if (ret)
return dev_err_probe(dev, ret, "failed to register resets\n");
return 0;
}
static const struct of_device_id of_k1_ccu_match[] = {
{
.compatible = "spacemit,k1-pll",
@ -1195,6 +1021,11 @@ static const struct of_device_id of_k1_ccu_match[] = {
};
MODULE_DEVICE_TABLE(of, of_k1_ccu_match);
static int k1_ccu_probe(struct platform_device *pdev)
{
return spacemit_ccu_probe(pdev, "spacemit,k1-pll");
}
static struct platform_driver k1_ccu_driver = {
.driver = {
.name = "spacemit,k1-ccu",
@ -1204,6 +1035,7 @@ static struct platform_driver k1_ccu_driver = {
};
module_platform_driver(k1_ccu_driver);
MODULE_IMPORT_NS("CLK_SPACEMIT");
MODULE_DESCRIPTION("SpacemiT K1 CCU driver");
MODULE_AUTHOR("Haylen Chu <heylenay@4d2.org>");
MODULE_LICENSE("GPL");

1487
drivers/clk/spacemit/ccu-k3.c Normal file
View File

File diff suppressed because it is too large Load Diff

177
drivers/clk/spacemit/ccu_common.c Normal file
View File

@ -0,0 +1,177 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/clk-provider.h>
#include <linux/device/devres.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <soc/spacemit/ccu.h>
#include "ccu_common.h"
static DEFINE_IDA(auxiliary_ids);
static int spacemit_ccu_register(struct device *dev,
struct regmap *regmap,
struct regmap *lock_regmap,
const struct spacemit_ccu_data *data)
{
struct clk_hw_onecell_data *clk_data;
int i, ret;
/* Nothing to do if the CCU does not implement any clocks */
if (!data->hws)
return 0;
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
clk_data->num = data->num;
for (i = 0; i < data->num; i++) {
struct clk_hw *hw = data->hws[i];
struct ccu_common *common;
const char *name;
if (!hw) {
clk_data->hws[i] = ERR_PTR(-ENOENT);
continue;
}
name = hw->init->name;
common = hw_to_ccu_common(hw);
common->regmap = regmap;
common->lock_regmap = lock_regmap;
ret = devm_clk_hw_register(dev, hw);
if (ret) {
dev_err(dev, "Cannot register clock %d - %s\n",
i, name);
return ret;
}
clk_data->hws[i] = hw;
}
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
if (ret)
dev_err(dev, "failed to add clock hardware provider (%d)\n", ret);
return ret;
}
static void spacemit_cadev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
ida_free(&auxiliary_ids, adev->id);
kfree(to_spacemit_ccu_adev(adev));
}
static void spacemit_adev_unregister(void *data)
{
struct auxiliary_device *adev = data;
auxiliary_device_delete(adev);
auxiliary_device_uninit(adev);
}
static int spacemit_ccu_reset_register(struct device *dev,
struct regmap *regmap,
const char *reset_name)
{
struct spacemit_ccu_adev *cadev;
struct auxiliary_device *adev;
int ret;
/* Nothing to do if the CCU does not implement a reset controller */
if (!reset_name)
return 0;
cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
if (!cadev)
return -ENOMEM;
cadev->regmap = regmap;
adev = &cadev->adev;
adev->name = reset_name;
adev->dev.parent = dev;
adev->dev.release = spacemit_cadev_release;
adev->dev.of_node = dev->of_node;
ret = ida_alloc(&auxiliary_ids, GFP_KERNEL);
if (ret < 0)
goto err_free_cadev;
adev->id = ret;
ret = auxiliary_device_init(adev);
if (ret)
goto err_free_aux_id;
ret = auxiliary_device_add(adev);
if (ret) {
auxiliary_device_uninit(adev);
return ret;
}
return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev);
err_free_aux_id:
ida_free(&auxiliary_ids, adev->id);
err_free_cadev:
kfree(cadev);
return ret;
}
int spacemit_ccu_probe(struct platform_device *pdev, const char *compat)
{
struct regmap *base_regmap, *lock_regmap = NULL;
const struct spacemit_ccu_data *data;
struct device *dev = &pdev->dev;
int ret;
base_regmap = device_node_to_regmap(dev->of_node);
if (IS_ERR(base_regmap))
return dev_err_probe(dev, PTR_ERR(base_regmap),
"failed to get regmap\n");
/*
* The lock status of PLLs locate in MPMU region, while PLLs themselves
* are in APBS region. Reference to MPMU syscon is required to check PLL
* status.
*/
if (compat && of_device_is_compatible(dev->of_node, compat)) {
struct device_node *mpmu = of_parse_phandle(dev->of_node,
"spacemit,mpmu", 0);
if (!mpmu)
return dev_err_probe(dev, -ENODEV,
"Cannot parse MPMU region\n");
lock_regmap = device_node_to_regmap(mpmu);
of_node_put(mpmu);
if (IS_ERR(lock_regmap))
return dev_err_probe(dev, PTR_ERR(lock_regmap),
"failed to get lock regmap\n");
}
data = of_device_get_match_data(dev);
ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data);
if (ret)
return dev_err_probe(dev, ret, "failed to register clocks\n");
ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name);
if (ret)
return dev_err_probe(dev, ret, "failed to register resets\n");
return 0;
}
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_probe, "CLK_SPACEMIT");
MODULE_DESCRIPTION("SpacemiT CCU common clock driver");
MODULE_LICENSE("GPL");

11
drivers/clk/spacemit/ccu_common.h
View File

@ -7,6 +7,8 @@
#ifndef _CCU_COMMON_H_
#define _CCU_COMMON_H_
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
struct ccu_common {
@ -24,6 +26,7 @@ struct ccu_common {
/* For PLL */
struct {
u32 reg_swcr1;
u32 reg_swcr2;
u32 reg_swcr3;
};
};
@ -36,6 +39,12 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
return container_of(hw, struct ccu_common, hw);
}
struct spacemit_ccu_data {
const char *reset_name;
struct clk_hw **hws;
size_t num;
};
#define ccu_read(c, reg) \
({ \
u32 tmp; \
@ -45,4 +54,6 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
#define ccu_update(c, reg, mask, val) \
regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val)
int spacemit_ccu_probe(struct platform_device *pdev, const char *compat);
#endif /* _CCU_COMMON_H_ */

1
drivers/clk/spacemit/ccu_ddn.c
View File

@ -84,3 +84,4 @@ const struct clk_ops spacemit_ccu_ddn_ops = {
.determine_rate = ccu_ddn_determine_rate,
.set_rate = ccu_ddn_set_rate,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_ddn_ops, "CLK_SPACEMIT");

21
drivers/clk/spacemit/ccu_mix.c
View File

@ -16,17 +16,19 @@
static void ccu_gate_disable(struct clk_hw *hw)
{
struct ccu_mix *mix = hw_to_ccu_mix(hw);
struct ccu_gate_config *gate = &mix->gate;
u32 val = gate->inverted ? gate->mask : 0;
ccu_update(&mix->common, ctrl, mix->gate.mask, 0);
ccu_update(&mix->common, ctrl, gate->mask, val);
}
static int ccu_gate_enable(struct clk_hw *hw)
{
struct ccu_mix *mix = hw_to_ccu_mix(hw);
struct ccu_gate_config *gate = &mix->gate;
u32 val = gate->inverted ? 0 : gate->mask;
ccu_update(&mix->common, ctrl, gate->mask, gate->mask);
ccu_update(&mix->common, ctrl, gate->mask, val);
return 0;
}
@ -34,8 +36,10 @@ static int ccu_gate_is_enabled(struct clk_hw *hw)
{
struct ccu_mix *mix = hw_to_ccu_mix(hw);
struct ccu_gate_config *gate = &mix->gate;
u32 tmp = ccu_read(&mix->common, ctrl) & gate->mask;
u32 val = gate->inverted ? 0 : gate->mask;
return (ccu_read(&mix->common, ctrl) & gate->mask) == gate->mask;
return !!(tmp == val);
}
static unsigned long ccu_factor_recalc_rate(struct clk_hw *hw,
@ -198,24 +202,28 @@ const struct clk_ops spacemit_ccu_gate_ops = {
.enable = ccu_gate_enable,
.is_enabled = ccu_gate_is_enabled,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_gate_ops, "CLK_SPACEMIT");
const struct clk_ops spacemit_ccu_factor_ops = {
.determine_rate = ccu_factor_determine_rate,
.recalc_rate = ccu_factor_recalc_rate,
.set_rate = ccu_factor_set_rate,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_factor_ops, "CLK_SPACEMIT");
const struct clk_ops spacemit_ccu_mux_ops = {
.determine_rate = ccu_mix_determine_rate,
.get_parent = ccu_mux_get_parent,
.set_parent = ccu_mux_set_parent,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_mux_ops, "CLK_SPACEMIT");
const struct clk_ops spacemit_ccu_div_ops = {
.determine_rate = ccu_mix_determine_rate,
.recalc_rate = ccu_div_recalc_rate,
.set_rate = ccu_mix_set_rate,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_div_ops, "CLK_SPACEMIT");
const struct clk_ops spacemit_ccu_factor_gate_ops = {
.disable = ccu_gate_disable,
@ -226,6 +234,7 @@ const struct clk_ops spacemit_ccu_factor_gate_ops = {
.recalc_rate = ccu_factor_recalc_rate,
.set_rate = ccu_factor_set_rate,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_factor_gate_ops, "CLK_SPACEMIT");
const struct clk_ops spacemit_ccu_mux_gate_ops = {
.disable = ccu_gate_disable,
@ -236,6 +245,7 @@ const struct clk_ops spacemit_ccu_mux_gate_ops = {
.get_parent = ccu_mux_get_parent,
.set_parent = ccu_mux_set_parent,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_mux_gate_ops, "CLK_SPACEMIT");
const struct clk_ops spacemit_ccu_div_gate_ops = {
.disable = ccu_gate_disable,
@ -246,6 +256,7 @@ const struct clk_ops spacemit_ccu_div_gate_ops = {
.recalc_rate = ccu_div_recalc_rate,
.set_rate = ccu_mix_set_rate,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_div_gate_ops, "CLK_SPACEMIT");
const struct clk_ops spacemit_ccu_mux_div_gate_ops = {
.disable = ccu_gate_disable,
@ -259,6 +270,7 @@ const struct clk_ops spacemit_ccu_mux_div_gate_ops = {
.recalc_rate = ccu_div_recalc_rate,
.set_rate = ccu_mix_set_rate,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_mux_div_gate_ops, "CLK_SPACEMIT");
const struct clk_ops spacemit_ccu_mux_div_ops = {
.get_parent = ccu_mux_get_parent,
@ -268,3 +280,4 @@ const struct clk_ops spacemit_ccu_mux_div_ops = {
.recalc_rate = ccu_div_recalc_rate,
.set_rate = ccu_mix_set_rate,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_mux_div_ops, "CLK_SPACEMIT");

12
drivers/clk/spacemit/ccu_mix.h
View File

@ -16,9 +16,11 @@
*
* @mask: Mask to enable the gate. Some clocks may have more than one bit
* set in this field.
* @inverted: Enable bit is inverted, 1 - disable clock, 0 - enable clock
*/
struct ccu_gate_config {
u32 mask;
bool inverted;
};
struct ccu_factor_config {
@ -48,6 +50,7 @@ struct ccu_mix {
#define CCU_FACTOR_INIT(_div, _mul) { .div = _div, .mul = _mul }
#define CCU_MUX_INIT(_shift, _width) { .shift = _shift, .width = _width }
#define CCU_DIV_INIT(_shift, _width) { .shift = _shift, .width = _width }
#define CCU_GATE_FLAGS_INIT(_mask, _inverted) { .mask = _mask, .inverted = _inverted }
#define CCU_PARENT_HW(_parent) { .hw = &_parent.common.hw }
#define CCU_PARENT_NAME(_name) { .fw_name = #_name }
@ -101,6 +104,15 @@ static struct ccu_mix _name = { \
} \
}
#define CCU_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _inverted, _flags) \
static struct ccu_mix _name = { \
.gate = CCU_GATE_FLAGS_INIT(_mask_gate, _inverted), \
.common = { \
.reg_ctrl = _reg_ctrl, \
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_gate_ops, _flags), \
} \
}
#define CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
_mul, _flags) \
static struct ccu_mix _name = { \

119
drivers/clk/spacemit/ccu_pll.c
View File

@ -17,6 +17,9 @@
#define PLL_SWCR3_EN ((u32)BIT(31))
#define PLL_SWCR3_MASK GENMASK(30, 0)
#define PLLA_SWCR2_EN ((u32)BIT(16))
#define PLLA_SWCR2_MASK GENMASK(15, 8)
static const struct ccu_pll_rate_tbl *ccu_pll_lookup_best_rate(struct ccu_pll *pll,
unsigned long rate)
{
@ -148,6 +151,110 @@ static int ccu_pll_init(struct clk_hw *hw)
return 0;
}
static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll)
{
struct ccu_pll_config *config = &pll->config;
const struct ccu_pll_rate_tbl *entry;
u32 i, swcr1, swcr2, swcr3;
swcr1 = ccu_read(&pll->common, swcr1);
swcr2 = ccu_read(&pll->common, swcr2);
swcr2 &= PLLA_SWCR2_MASK;
swcr3 = ccu_read(&pll->common, swcr3);
for (i = 0; i < config->tbl_num; i++) {
entry = &config->rate_tbl[i];
if (swcr1 == entry->swcr1 &&
swcr2 == entry->swcr2 &&
swcr3 == entry->swcr3)
return entry;
}
return NULL;
}
static void ccu_plla_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry)
{
struct ccu_common *common = &pll->common;
regmap_write(common->regmap, common->reg_swcr1, entry->swcr1);
regmap_write(common->regmap, common->reg_swcr3, entry->swcr3);
ccu_update(common, swcr2, PLLA_SWCR2_MASK, entry->swcr2);
}
static int ccu_plla_is_enabled(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);
return ccu_read(common, swcr2) & PLLA_SWCR2_EN;
}
static int ccu_plla_enable(struct clk_hw *hw)
{
struct ccu_pll *pll = hw_to_ccu_pll(hw);
struct ccu_common *common = &pll->common;
unsigned int tmp;
ccu_update(common, swcr2, PLLA_SWCR2_EN, PLLA_SWCR2_EN);
/* check lock status */
return regmap_read_poll_timeout_atomic(common->lock_regmap,
pll->config.reg_lock,
tmp,
tmp & pll->config.mask_lock,
PLL_DELAY_US, PLL_TIMEOUT_US);
}
static void ccu_plla_disable(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);
ccu_update(common, swcr2, PLLA_SWCR2_EN, 0);
}
/*
* PLLAs must be gated before changing rate, which is ensured by
* flag CLK_SET_RATE_GATE.
*/
static int ccu_plla_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_pll *pll = hw_to_ccu_pll(hw);
const struct ccu_pll_rate_tbl *entry;
entry = ccu_pll_lookup_best_rate(pll, rate);
ccu_plla_update_param(pll, entry);
return 0;
}
static unsigned long ccu_plla_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_pll *pll = hw_to_ccu_pll(hw);
const struct ccu_pll_rate_tbl *entry;
entry = ccu_plla_lookup_matched_entry(pll);
WARN_ON_ONCE(!entry);
return entry ? entry->rate : 0;
}
static int ccu_plla_init(struct clk_hw *hw)
{
struct ccu_pll *pll = hw_to_ccu_pll(hw);
if (ccu_plla_lookup_matched_entry(pll))
return 0;
ccu_plla_disable(hw);
ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
return 0;
}
const struct clk_ops spacemit_ccu_pll_ops = {
.init = ccu_pll_init,
.enable = ccu_pll_enable,
@ -157,3 +264,15 @@ const struct clk_ops spacemit_ccu_pll_ops = {
.determine_rate = ccu_pll_determine_rate,
.is_enabled = ccu_pll_is_enabled,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_pll_ops, "CLK_SPACEMIT");
const struct clk_ops spacemit_ccu_plla_ops = {
.init = ccu_plla_init,
.enable = ccu_plla_enable,
.disable = ccu_plla_disable,
.set_rate = ccu_plla_set_rate,
.recalc_rate = ccu_plla_recalc_rate,
.determine_rate = ccu_pll_determine_rate,
.is_enabled = ccu_plla_is_enabled,
};
EXPORT_SYMBOL_NS_GPL(spacemit_ccu_plla_ops, "CLK_SPACEMIT");

57
drivers/clk/spacemit/ccu_pll.h
View File

@ -16,14 +16,31 @@
* configuration.
*
* @rate: PLL rate
* @swcr1: Register value of PLLX_SW1_CTRL (PLLx_SWCR1).
* @swcr3: Register value of the PLLx_SW3_CTRL's lowest 31 bits of
* PLLx_SW3_CTRL (PLLx_SWCR3). This highest bit is for enabling
* the PLL and not contained in this field.
* @swcr1: Value of register PLLx_SW1_CTRL.
* @swcr2: Value of register PLLAx_SW2_CTRL.
* @swcr3: value of register PLLx_SW3_CTRL.
*
* See below tables for the register used in PPL/PPLA clocks
*
* Regular PLL type
* | Enable | swcr3 | PLLx_SW3_CTRL - BIT[31] |
* -----------------------------------------------
* | Config | swcr1 | PLLx_SW1_CTRL - BIT[31:0] |
* | | swcr2 | Not used |
* | | swcr3 | PLLx_SW3_CTRL - BIT[30:0] |
*
* Special PLL type A
* | Enable | swcr2 | PLLAx_SW2_CTRL - BIT[16] |
* -----------------------------------------------
* | Config | swcr1 | PLLAx_SW1_CTRL - BIT[31:0] |
* | | swcr2 | PLLAx_SW2_CTRL - BIT[15:8] |
* | | swcr3 | PLLAx_SW3_CTRL - BIT[31:0] |
*
*/
struct ccu_pll_rate_tbl {
unsigned long rate;
u32 swcr1;
u32 swcr2;
u32 swcr3;
};
@ -36,11 +53,19 @@ struct ccu_pll_config {
#define CCU_PLL_RATE(_rate, _swcr1, _swcr3) \
{ \
.rate = _rate, \
.rate = _rate, \
.swcr1 = _swcr1, \
.swcr3 = _swcr3, \
}
#define CCU_PLLA_RATE(_rate, _swcr1, _swcr2, _swcr3) \
{ \
.rate = _rate, \
.swcr1 = _swcr1, \
.swcr2 = _swcr2, \
.swcr3 = _swcr3, \
}
struct ccu_pll {
struct ccu_common common;
struct ccu_pll_config config;
@ -54,26 +79,37 @@ struct ccu_pll {
.mask_lock = (_mask_lock), \
}
#define CCU_PLL_HWINIT(_name, _flags) \
#define CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \
(&(struct clk_init_data) { \
.name = #_name, \
.ops = &spacemit_ccu_pll_ops, \
.ops = _ops, \
.parent_data = &(struct clk_parent_data) { .index = 0 }, \
.num_parents = 1, \
.flags = _flags, \
})
#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \
_mask_lock, _flags) \
#define CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \
_reg_lock, _mask_lock, _ops, _flags) \
static struct ccu_pll _name = { \
.config = CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock), \
.common = { \
.reg_swcr1 = _reg_swcr1, \
.reg_swcr2 = _reg_swcr2, \
.reg_swcr3 = _reg_swcr3, \
.hw.init = CCU_PLL_HWINIT(_name, _flags) \
.hw.init = CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \
} \
}
#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \
_mask_lock, _flags) \
CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, 0, _reg_swcr3, \
_reg_lock, _mask_lock, &spacemit_ccu_pll_ops, _flags)
#define CCU_PLLA_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \
_reg_lock, _mask_lock, _flags) \
CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \
_reg_lock, _mask_lock, &spacemit_ccu_plla_ops, _flags)
static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);
@ -82,5 +118,6 @@ static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw)
}
extern const struct clk_ops spacemit_ccu_pll_ops;
extern const struct clk_ops spacemit_ccu_plla_ops;
#endif

2
drivers/reset/reset-spacemit.c
View File

@ -278,7 +278,7 @@ static int spacemit_reset_probe(struct auxiliary_device *adev,
#define K1_AUX_DEV_ID(_unit) \
{ \
.name = "spacemit_ccu_k1." #_unit "-reset", \
.name = "spacemit_ccu.k1-" #_unit "-reset", \
.driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \
}

390
include/dt-bindings/clock/spacemit,k3-clocks.h Normal file
View File

@ -0,0 +1,390 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2025 SpacemiT Technology Co. Ltd
*/
#ifndef _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_
#define _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_
/* APBS (PLL) clocks */
#define CLK_PLL1 0
#define CLK_PLL2 1
#define CLK_PLL3 2
#define CLK_PLL4 3
#define CLK_PLL5 4
#define CLK_PLL6 5
#define CLK_PLL7 6
#define CLK_PLL8 7
#define CLK_PLL1_D2 8
#define CLK_PLL1_D3 9
#define CLK_PLL1_D4 10
#define CLK_PLL1_D5 11
#define CLK_PLL1_D6 12
#define CLK_PLL1_D7 13
#define CLK_PLL1_D8 14
#define CLK_PLL1_DX 15
#define CLK_PLL1_D64 16
#define CLK_PLL1_D10_AUD 17
#define CLK_PLL1_D100_AUD 18
#define CLK_PLL2_D1 19
#define CLK_PLL2_D2 20
#define CLK_PLL2_D3 21
#define CLK_PLL2_D4 22
#define CLK_PLL2_D5 23
#define CLK_PLL2_D6 24
#define CLK_PLL2_D7 25
#define CLK_PLL2_D8 26
#define CLK_PLL2_66 27
#define CLK_PLL2_33 28
#define CLK_PLL2_50 29
#define CLK_PLL2_25 30
#define CLK_PLL2_20 31
#define CLK_PLL2_D24_125 32
#define CLK_PLL2_D120_25 33
#define CLK_PLL3_D1 34
#define CLK_PLL3_D2 35
#define CLK_PLL3_D3 36
#define CLK_PLL3_D4 37
#define CLK_PLL3_D5 38
#define CLK_PLL3_D6 39
#define CLK_PLL3_D7 40
#define CLK_PLL3_D8 41
#define CLK_PLL4_D1 42
#define CLK_PLL4_D2 43
#define CLK_PLL4_D3 44
#define CLK_PLL4_D4 45
#define CLK_PLL4_D5 46
#define CLK_PLL4_D6 47
#define CLK_PLL4_D7 48
#define CLK_PLL4_D8 49
#define CLK_PLL5_D1 50
#define CLK_PLL5_D2 51
#define CLK_PLL5_D3 52
#define CLK_PLL5_D4 53
#define CLK_PLL5_D5 54
#define CLK_PLL5_D6 55
#define CLK_PLL5_D7 56
#define CLK_PLL5_D8 57
#define CLK_PLL6_D1 58
#define CLK_PLL6_D2 59
#define CLK_PLL6_D3 60
#define CLK_PLL6_D4 61
#define CLK_PLL6_D5 62
#define CLK_PLL6_D6 63
#define CLK_PLL6_D7 64
#define CLK_PLL6_D8 65
#define CLK_PLL6_80 66
#define CLK_PLL6_40 67
#define CLK_PLL6_20 68
#define CLK_PLL7_D1 69
#define CLK_PLL7_D2 70
#define CLK_PLL7_D3 71
#define CLK_PLL7_D4 72
#define CLK_PLL7_D5 73
#define CLK_PLL7_D6 74
#define CLK_PLL7_D7 75
#define CLK_PLL7_D8 76
#define CLK_PLL8_D1 77
#define CLK_PLL8_D2 78
#define CLK_PLL8_D3 79
#define CLK_PLL8_D4 80
#define CLK_PLL8_D5 81
#define CLK_PLL8_D6 82
#define CLK_PLL8_D7 83
#define CLK_PLL8_D8 84
/* MPMU clocks */
#define CLK_MPMU_PLL1_307P2 0
#define CLK_MPMU_PLL1_76P8 1
#define CLK_MPMU_PLL1_61P44 2
#define CLK_MPMU_PLL1_153P6 3
#define CLK_MPMU_PLL1_102P4 4
#define CLK_MPMU_PLL1_51P2 5
#define CLK_MPMU_PLL1_51P2_AP 6
#define CLK_MPMU_PLL1_57P6 7
#define CLK_MPMU_PLL1_25P6 8
#define CLK_MPMU_PLL1_12P8 9
#define CLK_MPMU_PLL1_12P8_WDT 10
#define CLK_MPMU_PLL1_6P4 11
#define CLK_MPMU_PLL1_3P2 12
#define CLK_MPMU_PLL1_1P6 13
#define CLK_MPMU_PLL1_0P8 14
#define CLK_MPMU_PLL1_409P6 15
#define CLK_MPMU_PLL1_204P8 16
#define CLK_MPMU_PLL1_491 17
#define CLK_MPMU_PLL1_245P76 18
#define CLK_MPMU_PLL1_614 19
#define CLK_MPMU_PLL1_47P26 20
#define CLK_MPMU_PLL1_31P5 21
#define CLK_MPMU_PLL1_819 22
#define CLK_MPMU_PLL1_1228 23
#define CLK_MPMU_APB 24
#define CLK_MPMU_SLOW_UART 25
#define CLK_MPMU_SLOW_UART1 26
#define CLK_MPMU_SLOW_UART2 27
#define CLK_MPMU_WDT 28
#define CLK_MPMU_WDT_BUS 29
#define CLK_MPMU_RIPC 30
#define CLK_MPMU_I2S_153P6 31
#define CLK_MPMU_I2S_153P6_BASE 32
#define CLK_MPMU_I2S_SYSCLK_SRC 33
#define CLK_MPMU_I2S1_SYSCLK 34
#define CLK_MPMU_I2S_BCLK 35
#define CLK_MPMU_I2S0_SYSCLK_SEL 36
#define CLK_MPMU_I2S2_SYSCLK_SEL 37
#define CLK_MPMU_I2S3_SYSCLK_SEL 38
#define CLK_MPMU_I2S4_SYSCLK_SEL 39
#define CLK_MPMU_I2S5_SYSCLK_SEL 40
#define CLK_MPMU_I2S0_SYSCLK_DIV 41
#define CLK_MPMU_I2S2_SYSCLK_DIV 42
#define CLK_MPMU_I2S3_SYSCLK_DIV 43
#define CLK_MPMU_I2S4_SYSCLK_DIV 44
#define CLK_MPMU_I2S5_SYSCLK_DIV 45
#define CLK_MPMU_I2S0_SYSCLK 46
#define CLK_MPMU_I2S2_SYSCLK 47
#define CLK_MPMU_I2S3_SYSCLK 48
#define CLK_MPMU_I2S4_SYSCLK 49
#define CLK_MPMU_I2S5_SYSCLK 50
/* APBC clocks */
#define CLK_APBC_UART0 0
#define CLK_APBC_UART2 1
#define CLK_APBC_UART3 2
#define CLK_APBC_UART4 3
#define CLK_APBC_UART5 4
#define CLK_APBC_UART6 5
#define CLK_APBC_UART7 6
#define CLK_APBC_UART8 7
#define CLK_APBC_UART9 8
#define CLK_APBC_UART10 9
#define CLK_APBC_UART0_BUS 10
#define CLK_APBC_UART2_BUS 11
#define CLK_APBC_UART3_BUS 12
#define CLK_APBC_UART4_BUS 13
#define CLK_APBC_UART5_BUS 14
#define CLK_APBC_UART6_BUS 15
#define CLK_APBC_UART7_BUS 16
#define CLK_APBC_UART8_BUS 17
#define CLK_APBC_UART9_BUS 18
#define CLK_APBC_UART10_BUS 19
#define CLK_APBC_GPIO 20
#define CLK_APBC_GPIO_BUS 21
#define CLK_APBC_PWM0 22
#define CLK_APBC_PWM1 23
#define CLK_APBC_PWM2 24
#define CLK_APBC_PWM3 25
#define CLK_APBC_PWM4 26
#define CLK_APBC_PWM5 27
#define CLK_APBC_PWM6 28
#define CLK_APBC_PWM7 29
#define CLK_APBC_PWM8 30
#define CLK_APBC_PWM9 31
#define CLK_APBC_PWM10 32
#define CLK_APBC_PWM11 33
#define CLK_APBC_PWM12 34
#define CLK_APBC_PWM13 35
#define CLK_APBC_PWM14 36
#define CLK_APBC_PWM15 37
#define CLK_APBC_PWM16 38
#define CLK_APBC_PWM17 39
#define CLK_APBC_PWM18 40
#define CLK_APBC_PWM19 41
#define CLK_APBC_PWM0_BUS 42
#define CLK_APBC_PWM1_BUS 43
#define CLK_APBC_PWM2_BUS 44
#define CLK_APBC_PWM3_BUS 45
#define CLK_APBC_PWM4_BUS 46
#define CLK_APBC_PWM5_BUS 47
#define CLK_APBC_PWM6_BUS 48
#define CLK_APBC_PWM7_BUS 49
#define CLK_APBC_PWM8_BUS 50
#define CLK_APBC_PWM9_BUS 51
#define CLK_APBC_PWM10_BUS 52
#define CLK_APBC_PWM11_BUS 53
#define CLK_APBC_PWM12_BUS 54
#define CLK_APBC_PWM13_BUS 55
#define CLK_APBC_PWM14_BUS 56
#define CLK_APBC_PWM15_BUS 57
#define CLK_APBC_PWM16_BUS 58
#define CLK_APBC_PWM17_BUS 59
#define CLK_APBC_PWM18_BUS 60
#define CLK_APBC_PWM19_BUS 61
#define CLK_APBC_SPI0_I2S_BCLK 62
#define CLK_APBC_SPI1_I2S_BCLK 63
#define CLK_APBC_SPI3_I2S_BCLK 64
#define CLK_APBC_SPI0 65
#define CLK_APBC_SPI1 66
#define CLK_APBC_SPI3 67
#define CLK_APBC_SPI0_BUS 68
#define CLK_APBC_SPI1_BUS 69
#define CLK_APBC_SPI3_BUS 70
#define CLK_APBC_RTC 71
#define CLK_APBC_RTC_BUS 72
#define CLK_APBC_TWSI0 73
#define CLK_APBC_TWSI1 74
#define CLK_APBC_TWSI2 75
#define CLK_APBC_TWSI4 76
#define CLK_APBC_TWSI5 77
#define CLK_APBC_TWSI6 78
#define CLK_APBC_TWSI8 79
#define CLK_APBC_TWSI0_BUS 80
#define CLK_APBC_TWSI1_BUS 81
#define CLK_APBC_TWSI2_BUS 82
#define CLK_APBC_TWSI4_BUS 83
#define CLK_APBC_TWSI5_BUS 84
#define CLK_APBC_TWSI6_BUS 85
#define CLK_APBC_TWSI8_BUS 86
#define CLK_APBC_TIMERS0 87
#define CLK_APBC_TIMERS1 88
#define CLK_APBC_TIMERS2 89
#define CLK_APBC_TIMERS3 90
#define CLK_APBC_TIMERS4 91
#define CLK_APBC_TIMERS5 92
#define CLK_APBC_TIMERS6 93
#define CLK_APBC_TIMERS7 94
#define CLK_APBC_TIMERS0_BUS 95
#define CLK_APBC_TIMERS1_BUS 96
#define CLK_APBC_TIMERS2_BUS 97
#define CLK_APBC_TIMERS3_BUS 98
#define CLK_APBC_TIMERS4_BUS 99
#define CLK_APBC_TIMERS5_BUS 100
#define CLK_APBC_TIMERS6_BUS 101
#define CLK_APBC_TIMERS7_BUS 102
#define CLK_APBC_AIB 103
#define CLK_APBC_AIB_BUS 104
#define CLK_APBC_ONEWIRE 105
#define CLK_APBC_ONEWIRE_BUS 106
#define CLK_APBC_I2S0_BCLK 107
#define CLK_APBC_I2S1_BCLK 108
#define CLK_APBC_I2S2_BCLK 109
#define CLK_APBC_I2S3_BCLK 110
#define CLK_APBC_I2S4_BCLK 111
#define CLK_APBC_I2S5_BCLK 112
#define CLK_APBC_I2S0 113
#define CLK_APBC_I2S1 114
#define CLK_APBC_I2S2 115
#define CLK_APBC_I2S3 116
#define CLK_APBC_I2S4 117
#define CLK_APBC_I2S5 118
#define CLK_APBC_I2S0_BUS 119
#define CLK_APBC_I2S1_BUS 120
#define CLK_APBC_I2S2_BUS 121
#define CLK_APBC_I2S3_BUS 122
#define CLK_APBC_I2S4_BUS 123
#define CLK_APBC_I2S5_BUS 124
#define CLK_APBC_DRO 125
#define CLK_APBC_IR0 126
#define CLK_APBC_IR1 127
#define CLK_APBC_TSEN 128
#define CLK_APBC_TSEN_BUS 129
#define CLK_APBC_IPC_AP2RCPU 130
#define CLK_APBC_IPC_AP2RCPU_BUS 131
#define CLK_APBC_CAN0 132
#define CLK_APBC_CAN1 133
#define CLK_APBC_CAN2 134
#define CLK_APBC_CAN3 135
#define CLK_APBC_CAN4 136
#define CLK_APBC_CAN0_BUS 137
#define CLK_APBC_CAN1_BUS 138
#define CLK_APBC_CAN2_BUS 139
#define CLK_APBC_CAN3_BUS 140
#define CLK_APBC_CAN4_BUS 141
/* APMU clocks */
#define CLK_APMU_AXICLK 0
#define CLK_APMU_CCI550 1
#define CLK_APMU_CPU_C0_CORE 2
#define CLK_APMU_CPU_C1_CORE 3
#define CLK_APMU_CPU_C2_CORE 4
#define CLK_APMU_CPU_C3_CORE 5
#define CLK_APMU_CCIC2PHY 6
#define CLK_APMU_CCIC3PHY 7
#define CLK_APMU_CSI 8
#define CLK_APMU_ISP_BUS 9
#define CLK_APMU_D1P_1228P8 10
#define CLK_APMU_D1P_819P2 11
#define CLK_APMU_D1P_614P4 12
#define CLK_APMU_D1P_491P52 13
#define CLK_APMU_D1P_409P6 14
#define CLK_APMU_D1P_307P2 15
#define CLK_APMU_D1P_245P76 16
#define CLK_APMU_V2D 17
#define CLK_APMU_DSI_ESC 18
#define CLK_APMU_LCD_HCLK 19
#define CLK_APMU_LCD_DSC 20
#define CLK_APMU_LCD_PXCLK 21
#define CLK_APMU_LCD_MCLK 22
#define CLK_APMU_CCIC_4X 23
#define CLK_APMU_CCIC1PHY 24
#define CLK_APMU_SC2_HCLK 25
#define CLK_APMU_SDH_AXI 26
#define CLK_APMU_SDH0 27
#define CLK_APMU_SDH1 28
#define CLK_APMU_SDH2 29
#define CLK_APMU_USB2_BUS 30
#define CLK_APMU_USB3_PORTA_BUS 31
#define CLK_APMU_USB3_PORTB_BUS 32
#define CLK_APMU_USB3_PORTC_BUS 33
#define CLK_APMU_USB3_PORTD_BUS 34
#define CLK_APMU_QSPI 35
#define CLK_APMU_QSPI_BUS 36
#define CLK_APMU_DMA 37
#define CLK_APMU_AES_WTM 38
#define CLK_APMU_VPU 39
#define CLK_APMU_DTC 40
#define CLK_APMU_GPU 41
#define CLK_APMU_MC_AHB 42
#define CLK_APMU_TOP_DCLK 43
#define CLK_APMU_UCIE 44
#define CLK_APMU_UCIE_SBCLK 45
#define CLK_APMU_RCPU 46
#define CLK_APMU_DSI4LN2_DSI_ESC 47
#define CLK_APMU_DSI4LN2_LCD_DSC 48
#define CLK_APMU_DSI4LN2_LCD_PXCLK 49
#define CLK_APMU_DSI4LN2_LCD_MCLK 50
#define CLK_APMU_DSI4LN2_DPU_ACLK 51
#define CLK_APMU_DPU_ACLK 52
#define CLK_APMU_UFS_ACLK 53
#define CLK_APMU_EDP0_PXCLK 54
#define CLK_APMU_EDP1_PXCLK 55
#define CLK_APMU_PCIE_PORTA_MSTE 56
#define CLK_APMU_PCIE_PORTA_SLV 57
#define CLK_APMU_PCIE_PORTB_MSTE 58
#define CLK_APMU_PCIE_PORTB_SLV 59
#define CLK_APMU_PCIE_PORTC_MSTE 60
#define CLK_APMU_PCIE_PORTC_SLV 61
#define CLK_APMU_PCIE_PORTD_MSTE 62
#define CLK_APMU_PCIE_PORTD_SLV 63
#define CLK_APMU_PCIE_PORTE_MSTE 64
#define CLK_APMU_PCIE_PORTE_SLV 65
#define CLK_APMU_EMAC0_BUS 66
#define CLK_APMU_EMAC0_REF 67
#define CLK_APMU_EMAC0_1588 68
#define CLK_APMU_EMAC0_RGMII_TX 69
#define CLK_APMU_EMAC1_BUS 70
#define CLK_APMU_EMAC1_REF 71
#define CLK_APMU_EMAC1_1588 72
#define CLK_APMU_EMAC1_RGMII_TX 73
#define CLK_APMU_EMAC2_BUS 74
#define CLK_APMU_EMAC2_REF 75
#define CLK_APMU_EMAC2_1588 76
#define CLK_APMU_EMAC2_RGMII_TX 77
#define CLK_APMU_ESPI_SCLK_SRC 78
#define CLK_APMU_ESPI_SCLK 79
#define CLK_APMU_ESPI_MCLK 80
#define CLK_APMU_CAM_SRC1 81
#define CLK_APMU_CAM_SRC2 82
#define CLK_APMU_CAM_SRC3 83
#define CLK_APMU_CAM_SRC4 84
#define CLK_APMU_ISIM_VCLK0 85
#define CLK_APMU_ISIM_VCLK1 86
#define CLK_APMU_ISIM_VCLK2 87
#define CLK_APMU_ISIM_VCLK3 88
/* DCIU clocks */
#define CLK_DCIU_HDMA 0
#define CLK_DCIU_DMA350 1
#define CLK_DCIU_C2_TCM_PIPE 2
#define CLK_DCIU_C3_TCM_PIPE 3
#endif /* _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ */

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include/soc/spacemit/ccu.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_SPACEMIT_CCU_H__
#define __SOC_SPACEMIT_CCU_H__
#include <linux/auxiliary_bus.h>
#include <linux/regmap.h>
/* Auxiliary device used to represent a CCU reset controller */
struct spacemit_ccu_adev {
struct auxiliary_device adev;
struct regmap *regmap;
};
static inline struct spacemit_ccu_adev *
to_spacemit_ccu_adev(struct auxiliary_device *adev)
{
return container_of(adev, struct spacemit_ccu_adev, adev);
}
#endif /* __SOC_SPACEMIT_CCU_H__ */

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include/soc/spacemit/k1-syscon.h
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#ifndef __SOC_K1_SYSCON_H__
#define __SOC_K1_SYSCON_H__
/* Auxiliary device used to represent a CCU reset controller */
struct spacemit_ccu_adev {
struct auxiliary_device adev;
struct regmap *regmap;
};
static inline struct spacemit_ccu_adev *
to_spacemit_ccu_adev(struct auxiliary_device *adev)
{
return container_of(adev, struct spacemit_ccu_adev, adev);
}
#include "ccu.h"
/* APBS register offset */
#define APBS_PLL1_SWCR1 0x100

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/* SPDX-License-Identifier: GPL-2.0-only */
/* SpacemiT clock and reset driver definitions for the K3 SoC */
#ifndef __SOC_K3_SYSCON_H__
#define __SOC_K3_SYSCON_H__
#include "ccu.h"
/* APBS register offset */
#define APBS_PLL1_SWCR1 0x100
#define APBS_PLL1_SWCR2 0x104
#define APBS_PLL1_SWCR3 0x108
#define APBS_PLL2_SWCR1 0x118
#define APBS_PLL2_SWCR2 0x11c
#define APBS_PLL2_SWCR3 0x120
#define APBS_PLL3_SWCR1 0x124
#define APBS_PLL3_SWCR2 0x128
#define APBS_PLL3_SWCR3 0x12c
#define APBS_PLL4_SWCR1 0x130
#define APBS_PLL4_SWCR2 0x134
#define APBS_PLL4_SWCR3 0x138
#define APBS_PLL5_SWCR1 0x13c
#define APBS_PLL5_SWCR2 0x140
#define APBS_PLL5_SWCR3 0x144
#define APBS_PLL6_SWCR1 0x148
#define APBS_PLL6_SWCR2 0x14c
#define APBS_PLL6_SWCR3 0x150
#define APBS_PLL7_SWCR1 0x158
#define APBS_PLL7_SWCR2 0x15c
#define APBS_PLL7_SWCR3 0x160
#define APBS_PLL8_SWCR1 0x180
#define APBS_PLL8_SWCR2 0x184
#define APBS_PLL8_SWCR3 0x188
/* MPMU register offset */
#define MPMU_FCCR 0x0008
#define MPMU_POSR 0x0010
#define POSR_PLL1_LOCK BIT(24)
#define POSR_PLL2_LOCK BIT(25)
#define POSR_PLL3_LOCK BIT(26)
#define POSR_PLL4_LOCK BIT(27)
#define POSR_PLL5_LOCK BIT(28)
#define POSR_PLL6_LOCK BIT(29)
#define POSR_PLL7_LOCK BIT(30)
#define POSR_PLL8_LOCK BIT(31)
#define MPMU_SUCCR 0x0014
#define MPMU_ISCCR 0x0044
#define MPMU_WDTPCR 0x0200
#define MPMU_RIPCCR 0x0210
#define MPMU_ACGR 0x1024
#define MPMU_APBCSCR 0x1050
#define MPMU_SUCCR_1 0x10b0
#define MPMU_I2S0_SYSCLK 0x1100
#define MPMU_I2S2_SYSCLK 0x1104
#define MPMU_I2S3_SYSCLK 0x1108
#define MPMU_I2S4_SYSCLK 0x110c
#define MPMU_I2S5_SYSCLK 0x1110
#define MPMU_I2S_SYSCLK_CTRL 0x1114
/* APBC register offset */
#define APBC_UART0_CLK_RST 0x00
#define APBC_UART2_CLK_RST 0x04
#define APBC_GPIO_CLK_RST 0x08
#define APBC_PWM0_CLK_RST 0x0c
#define APBC_PWM1_CLK_RST 0x10
#define APBC_PWM2_CLK_RST 0x14
#define APBC_PWM3_CLK_RST 0x18
#define APBC_TWSI8_CLK_RST 0x20
#define APBC_UART3_CLK_RST 0x24
#define APBC_RTC_CLK_RST 0x28
#define APBC_TWSI0_CLK_RST 0x2c
#define APBC_TWSI1_CLK_RST 0x30
#define APBC_TIMERS0_CLK_RST 0x34
#define APBC_TWSI2_CLK_RST 0x38
#define APBC_AIB_CLK_RST 0x3c
#define APBC_TWSI4_CLK_RST 0x40
#define APBC_TIMERS1_CLK_RST 0x44
#define APBC_ONEWIRE_CLK_RST 0x48
#define APBC_TWSI5_CLK_RST 0x4c
#define APBC_DRO_CLK_RST 0x58
#define APBC_IR0_CLK_RST 0x5c
#define APBC_IR1_CLK_RST 0x1c
#define APBC_TWSI6_CLK_RST 0x60
#define APBC_COUNTER_CLK_SEL 0x64
#define APBC_TSEN_CLK_RST 0x6c
#define APBC_UART4_CLK_RST 0x70
#define APBC_UART5_CLK_RST 0x74
#define APBC_UART6_CLK_RST 0x78
#define APBC_SSP3_CLK_RST 0x7c
#define APBC_SSPA0_CLK_RST 0x80
#define APBC_SSPA1_CLK_RST 0x84
#define APBC_SSPA2_CLK_RST 0x88
#define APBC_SSPA3_CLK_RST 0x8c
#define APBC_IPC_AP2AUD_CLK_RST 0x90
#define APBC_UART7_CLK_RST 0x94
#define APBC_UART8_CLK_RST 0x98
#define APBC_UART9_CLK_RST 0x9c
#define APBC_CAN0_CLK_RST 0xa0
#define APBC_CAN1_CLK_RST 0xa4
#define APBC_PWM4_CLK_RST 0xa8
#define APBC_PWM5_CLK_RST 0xac
#define APBC_PWM6_CLK_RST 0xb0
#define APBC_PWM7_CLK_RST 0xb4
#define APBC_PWM8_CLK_RST 0xb8
#define APBC_PWM9_CLK_RST 0xbc
#define APBC_PWM10_CLK_RST 0xc0
#define APBC_PWM11_CLK_RST 0xc4
#define APBC_PWM12_CLK_RST 0xc8
#define APBC_PWM13_CLK_RST 0xcc
#define APBC_PWM14_CLK_RST 0xd0
#define APBC_PWM15_CLK_RST 0xd4
#define APBC_PWM16_CLK_RST 0xd8
#define APBC_PWM17_CLK_RST 0xdc
#define APBC_PWM18_CLK_RST 0xe0
#define APBC_PWM19_CLK_RST 0xe4
#define APBC_TIMERS2_CLK_RST 0x11c
#define APBC_TIMERS3_CLK_RST 0x120
#define APBC_TIMERS4_CLK_RST 0x124
#define APBC_TIMERS5_CLK_RST 0x128
#define APBC_TIMERS6_CLK_RST 0x12c
#define APBC_TIMERS7_CLK_RST 0x130
#define APBC_CAN2_CLK_RST 0x148
#define APBC_CAN3_CLK_RST 0x14c
#define APBC_CAN4_CLK_RST 0x150
#define APBC_UART10_CLK_RST 0x154
#define APBC_SSP0_CLK_RST 0x158
#define APBC_SSP1_CLK_RST 0x15c
#define APBC_SSPA4_CLK_RST 0x160
#define APBC_SSPA5_CLK_RST 0x164
/* APMU register offset */
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
#define APMU_ISP_CLK_RES_CTRL 0x038
#define APMU_PMU_CLK_GATE_CTRL 0x040
#define APMU_LCD_CLK_RES_CTRL1 0x044
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
#define APMU_LCD_CLK_RES_CTRL2 0x04c
#define APMU_CCIC_CLK_RES_CTRL 0x050
#define APMU_SDH0_CLK_RES_CTRL 0x054
#define APMU_SDH1_CLK_RES_CTRL 0x058
#define APMU_USB_CLK_RES_CTRL 0x05c
#define APMU_QSPI_CLK_RES_CTRL 0x060
#define APMU_DMA_CLK_RES_CTRL 0x064
#define APMU_AES_CLK_RES_CTRL 0x068
#define APMU_MCB_CLK_RES_CTRL 0x06c
#define APMU_VPU_CLK_RES_CTRL 0x0a4
#define APMU_DTC_CLK_RES_CTRL 0x0ac
#define APMU_GPU_CLK_RES_CTRL 0x0cc
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
#define APMU_PMUA_MC_CTRL 0x0e8
#define APMU_PMU_CC2_AP 0x100
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
#define APMU_UCIE_CTRL 0x11c
#define APMU_RCPU_CLK_RES_CTRL 0x14c
#define APMU_TOP_DCLK_CTRL 0x158
#define APMU_LCD_EDP_CTRL 0x23c
#define APMU_UFS_CLK_RES_CTRL 0x268
#define APMU_LCD_CLK_RES_CTRL3 0x26c
#define APMU_LCD_CLK_RES_CTRL4 0x270
#define APMU_LCD_CLK_RES_CTRL5 0x274
#define APMU_CCI550_CLK_CTRL 0x300
#define APMU_ACLK_CLK_CTRL 0x388
#define APMU_CPU_C0_CLK_CTRL 0x38C
#define APMU_CPU_C1_CLK_CTRL 0x390
#define APMU_CPU_C2_CLK_CTRL 0x394
#define APMU_CPU_C3_CLK_CTRL 0x208
#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0
#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8
#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0
#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0
#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
#define APMU_EMAC2_CLK_RES_CTRL 0x248
#define APMU_ESPI_CLK_RES_CTRL 0x240
#define APMU_SNR_ISIM_VCLK_CTRL 0x3f8
/* DCIU register offsets */
#define DCIU_DMASYS_CLK_EN 0x234
#define DCIU_DMASYS_SDMA_CLK_EN 0x238
#define DCIU_C2_TCM_PIPE_CLK 0x244
#define DCIU_C3_TCM_PIPE_CLK 0x248
#define DCIU_DMASYS_S0_RSTN 0x204
#define DCIU_DMASYS_S1_RSTN 0x208
#define DCIU_DMASYS_A0_RSTN 0x20C
#define DCIU_DMASYS_A1_RSTN 0x210
#define DCIU_DMASYS_A2_RSTN 0x214
#define DCIU_DMASYS_A3_RSTN 0x218
#define DCIU_DMASYS_A4_RSTN 0x21C
#define DCIU_DMASYS_A5_RSTN 0x220
#define DCIU_DMASYS_A6_RSTN 0x224
#define DCIU_DMASYS_A7_RSTN 0x228
#define DCIU_DMASYS_RSTN 0x22C
#define DCIU_DMASYS_SDMA_RSTN 0x230
/* RCPU SYSCTRL register offsets */
#define RCPU_CAN_CLK_RST 0x4c
#define RCPU_CAN1_CLK_RST 0xF0
#define RCPU_CAN2_CLK_RST 0xF4
#define RCPU_CAN3_CLK_RST 0xF8
#define RCPU_CAN4_CLK_RST 0xFC
#define RCPU_IRC_CLK_RST 0x48
#define RCPU_IRC1_CLK_RST 0xEC
#define RCPU_GMAC_CLK_RST 0xE4
#define RCPU_ESPI_CLK_RST 0xDC
#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70
#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44
/* RCPU UARTCTRL register offsets */
#define RCPU1_UART0_CLK_RST 0x00
#define RCPU1_UART1_CLK_RST 0x04
#define RCPU1_UART2_CLK_RST 0x08
#define RCPU1_UART3_CLK_RST 0x0c
#define RCPU1_UART4_CLK_RST 0x10
#define RCPU1_UART5_CLK_RST 0x14
/* RCPU I2SCTRL register offsets */
#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60
#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64
#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68
#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C
#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44
#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54
/* RCPU SPICTRL register offsets */
#define RCPU3_SSP0_CLK_RST 0x00
#define RCPU3_SSP1_CLK_RST 0x04
#define RCPU3_PWR_SSP_CLK_RST 0x08
/* RCPU I2CCTRL register offsets */
#define RCPU4_I2C0_CLK_RST 0x00
#define RCPU4_I2C1_CLK_RST 0x04
#define RCPU4_PWR_I2C_CLK_RST 0x08
/* RPMU register offsets */
#define RCPU5_AON_PER_CLK_RST_CTRL 0x2C
#define RCPU5_TIMER1_CLK_RST 0x4C
#define RCPU5_TIMER2_CLK_RST 0x70
#define RCPU5_TIMER3_CLK_RST 0x78
#define RCPU5_TIMER4_CLK_RST 0x7C
#define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74
#define RCPU5_RCPU_BUS_CLK_CTRL 0xC0
#define RCPU5_RT24_CORE0_CLK_CTRL 0xC4
#define RCPU5_RT24_CORE1_CLK_CTRL 0xC8
#define RCPU5_RT24_CORE0_SW_RESET 0xCC
#define RCPU5_RT24_CORE1_SW_RESET 0xD0
/* RCPU PWMCTRL register offsets */
#define RCPU6_PWM0_CLK_RST 0x00
#define RCPU6_PWM1_CLK_RST 0x04
#define RCPU6_PWM2_CLK_RST 0x08
#define RCPU6_PWM3_CLK_RST 0x0c
#define RCPU6_PWM4_CLK_RST 0x10
#define RCPU6_PWM5_CLK_RST 0x14
#define RCPU6_PWM6_CLK_RST 0x18
#define RCPU6_PWM7_CLK_RST 0x1c
#define RCPU6_PWM8_CLK_RST 0x20
#define RCPU6_PWM9_CLK_RST 0x24
/* APBC2 SEC register offsets */
#define APBC2_UART1_CLK_RST 0x00
#define APBC2_SSP2_CLK_RST 0x04
#define APBC2_TWSI3_CLK_RST 0x08
#define APBC2_RTC_CLK_RST 0x0c
#define APBC2_TIMERS_CLK_RST 0x10
#define APBC2_GPIO_CLK_RST 0x1c
#endif /* __SOC_K3_SYSCON_H__ */