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Merge branch 'octeontx2-quiesce-stale-mailbox-irq-state-before-request_irq'

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Runyu Xiao says:

====================
octeontx2: quiesce stale mailbox IRQ state before request_irq()

Both OTX2 mailbox registration paths currently install their IRQ
handlers before clearing stale local mailbox interrupt state, even
though the code comments already say that the clear is needed first to
avoid spurious interrupts.

This issue was found by our static analysis tool and manually audited on
Linux v6.18.21. Directed QEMU no-device validation further showed that
the real PF and VF mailbox handlers are already reachable in that
pre-clear window and can touch the same mailbox and workqueue carrier
before local quiesce has completed.

This series keeps the change minimal:

- clear stale mailbox interrupt state before request_irq()
- keep interrupt enabling after the handler is installed

That closes the early-IRQ window without introducing a new
enable-before-handler window.

Patch 1 fixes the PF mailbox registration path.
Patch 2 fixes the VF mailbox registration path.

Build-tested by compiling otx2_pf.o and otx2_vf.o.

No OTX2 hardware was available for end-to-end runtime testing.
====================

Link: https://patch.msgid.link/20260611160014.3202224-1-runyu.xiao@seu.edu.cn
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2026-06-15 12:47:20 -07:00
commit 62821d4819
2 changed files with 19 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
View File

@ -1119,9 +1119,16 @@ int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
{
struct otx2_hw *hw = &pf->hw;
struct msg_req *req;
u64 mbox_int_mask;
char *irq_name;
int err;
mbox_int_mask = !is_cn20k(pf->pdev) ? BIT_ULL(0) :
BIT_ULL(0) | BIT_ULL(1);
/* Clear stale mailbox interrupt state before installing the handler. */
otx2_write64(pf, RVU_PF_INT, mbox_int_mask);
/* Register mailbox interrupt handler */
if (!is_cn20k(pf->pdev)) {
irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE];
@ -1147,17 +1154,8 @@ int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
return err;
}
/* Enable mailbox interrupt for msgs coming from AF.
* First clear to avoid spurious interrupts, if any.
*/
if (!is_cn20k(pf->pdev)) {
otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
} else {
otx2_write64(pf, RVU_PF_INT, BIT_ULL(0) | BIT_ULL(1));
otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0) |
BIT_ULL(1));
}
/* Enable mailbox interrupt for msgs coming from AF. */
otx2_write64(pf, RVU_PF_INT_ENA_W1S, mbox_int_mask);
if (!probe_af)
return 0;

22
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
View File

@ -251,9 +251,17 @@ static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf)
{
struct otx2_hw *hw = &vf->hw;
struct msg_req *req;
u64 mbox_int_mask;
char *irq_name;
int err;
mbox_int_mask = !is_cn20k(vf->pdev) ? BIT_ULL(0) :
BIT_ULL(0) | BIT_ULL(1) |
BIT_ULL(2) | BIT_ULL(3);
/* Clear stale mailbox interrupt state before installing the handler. */
otx2_write64(vf, RVU_VF_INT, mbox_int_mask);
/* Register mailbox interrupt handler */
irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE];
snprintf(irq_name, NAME_SIZE, "RVUVF%d AFVF Mbox", ((vf->pcifunc &
@ -274,18 +282,8 @@ static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf)
return err;
}
/* Enable mailbox interrupt for msgs coming from PF.
* First clear to avoid spurious interrupts, if any.
*/
if (!is_cn20k(vf->pdev)) {
otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0));
} else {
otx2_write64(vf, RVU_VF_INT, BIT_ULL(0) | BIT_ULL(1) |
BIT_ULL(2) | BIT_ULL(3));
otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0) |
BIT_ULL(1) | BIT_ULL(2) | BIT_ULL(3));
}
/* Enable mailbox interrupt for msgs coming from PF. */
otx2_write64(vf, RVU_VF_INT_ENA_W1S, mbox_int_mask);
if (!probe_pf)
return 0;