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arm64: dts: renesas: rzg2: Add boot phase tags

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bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT.  Add bootph-all for all nodes that are used in the
bootloader on Renesas RZ/G2 SoCs.

All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.

Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Marek Vasut 2025-02-09 19:05:06 +01:00 committed by Geert Uytterhoeven
parent 399f14ff66
commit 624b2a23d4
7 changed files with 34 additions and 0 deletions
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1
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
View File

@ -282,6 +282,7 @@ &scif_clk {
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};

1
arch/arm64/boot/dts/renesas/hihope-common.dtsi
View File

@ -289,6 +289,7 @@ &rwdt {
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};

8
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -215,6 +215,7 @@ extal_clk: extal {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
bootph-all;
};
extalr_clk: extalr {
@ -222,6 +223,7 @@ extalr_clk: extalr {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
bootph-all;
};
/* External PCIe clock - can be overridden by the board */
@ -262,6 +264,8 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -400,6 +404,7 @@ gpio7: gpio@e6055800 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774a1";
reg = <0 0xe6060000 0 0x50c>;
bootph-all;
};
cmt0: timer@e60f0000 {
@ -480,11 +485,13 @@ cpg: clock-controller@e6150000 {
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
bootph-all;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a774a1-rst";
reg = <0 0xe6160000 0 0x018c>;
bootph-all;
};
sysc: system-controller@e6180000 {
@ -2785,6 +2792,7 @@ port@1 {
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
bootph-all;
};
};

8
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@ -108,6 +108,7 @@ extal_clk: extal {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
bootph-all;
};
extalr_clk: extalr {
@ -115,6 +116,7 @@ extalr_clk: extalr {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
bootph-all;
};
/* External PCIe clock - can be overridden by the board */
@ -146,6 +148,8 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -284,6 +288,7 @@ gpio7: gpio@e6055800 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774b1";
reg = <0 0xe6060000 0 0x50c>;
bootph-all;
};
cmt0: timer@e60f0000 {
@ -364,11 +369,13 @@ cpg: clock-controller@e6150000 {
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
bootph-all;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a774b1-rst";
reg = <0 0xe6160000 0 0x0200>;
bootph-all;
};
sysc: system-controller@e6180000 {
@ -2661,6 +2668,7 @@ port@1 {
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
bootph-all;
};
};

1
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
View File

@ -378,6 +378,7 @@ &rwdt {
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};

7
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -107,6 +107,7 @@ extal_clk: extal {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
bootph-all;
};
/* External PCIe clock - can be overridden by the board */
@ -138,6 +139,8 @@ scif_clk: scif {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -261,6 +264,7 @@ gpio6: gpio@e6055400 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774c0";
reg = <0 0xe6060000 0 0x508>;
bootph-all;
};
cmt0: timer@e60f0000 {
@ -341,11 +345,13 @@ cpg: clock-controller@e6150000 {
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
bootph-all;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a774c0-rst";
reg = <0 0xe6160000 0 0x0200>;
bootph-all;
};
sysc: system-controller@e6180000 {
@ -1957,6 +1963,7 @@ port@1 {
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
bootph-all;
};
};

8
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@ -277,6 +277,7 @@ extal_clk: extal {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
bootph-all;
};
extalr_clk: extalr {
@ -284,6 +285,7 @@ extalr_clk: extalr {
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
bootph-all;
};
/* External PCIe clock - can be overridden by the board */
@ -326,6 +328,8 @@ scif_clk: scif {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
bootph-all;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -464,6 +468,7 @@ gpio7: gpio@e6055800 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774e1";
reg = <0 0xe6060000 0 0x50c>;
bootph-all;
};
cmt0: timer@e60f0000 {
@ -544,11 +549,13 @@ cpg: clock-controller@e6150000 {
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
bootph-all;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a774e1-rst";
reg = <0 0xe6160000 0 0x0200>;
bootph-all;
};
sysc: system-controller@e6180000 {
@ -2917,6 +2924,7 @@ port@1 {
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
bootph-all;
};
};