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drm/amd/display: Revert "Migrate DCCG register access from hwseq to dccg component."

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[Why & How]
This reverts commit 949adb4789, which
causes regressions related to HDCP when resuming from S3.

Reviewed-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Nicholas Carbones <ncarbone@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Carbones 2026-01-28 12:28:54 -05:00 committed by Alex Deucher
parent 3303aa64e7
commit 6246c12f52
12 changed files with 49 additions and 98 deletions
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54
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
View File

@ -131,54 +131,6 @@ void dccg2_otg_drop_pixel(struct dccg *dccg,
void dccg2_init(struct dccg *dccg)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
/* Hardcoded register values for DCN20
* These are specific to 100Mhz refclk
* Different ASICs with different refclk may override this in their own init
*/
REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264);
REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0);
REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c);
if (REG(REFCLK_CNTL))
REG_WRITE(REFCLK_CNTL, 0);
}
void dccg2_refclk_setup(struct dccg *dccg)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
/* REFCLK programming that must occur after hubbub initialization */
if (REG(REFCLK_CNTL))
REG_WRITE(REFCLK_CNTL, 0);
}
bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464;
}
void dccg2_allow_clock_gating(struct dccg *dccg, bool allow)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
if (allow) {
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
} else {
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF);
}
}
void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1);
}
static const struct dccg_funcs dccg2_funcs = {
@ -187,11 +139,7 @@ static const struct dccg_funcs dccg2_funcs = {
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
.otg_add_pixel = dccg2_otg_add_pixel,
.otg_drop_pixel = dccg2_otg_drop_pixel,
.dccg_init = dccg2_init,
.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
.allow_clock_gating = dccg2_allow_clock_gating,
.enable_memory_low_power = dccg2_enable_memory_low_power,
.is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done
.dccg_init = dccg2_init
};
struct dccg *dccg2_create(

18
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
View File

@ -46,9 +46,7 @@
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
SR(DCCG_GATE_DISABLE_CNTL),\
SR(DCCG_GATE_DISABLE_CNTL2)
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
#define DCCG_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@ -83,8 +81,7 @@
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\
DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
@ -133,8 +130,7 @@
type DISPCLK_CHG_FWD_CORR_DISABLE;\
type DISPCLK_FREQ_CHANGE_CNTL;\
type OTG_ADD_PIXEL[MAX_PIPES];\
type OTG_DROP_PIXEL[MAX_PIPES];\
type DC_MEM_GLOBAL_PWR_REQ_DIS;
type OTG_DROP_PIXEL[MAX_PIPES];
#define DCCG3_REG_FIELD_LIST(type) \
type HDMICHARCLK0_EN;\
@ -519,14 +515,6 @@ void dccg2_otg_drop_pixel(struct dccg *dccg,
void dccg2_init(struct dccg *dccg);
void dccg2_refclk_setup(struct dccg *dccg);
bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg);
void dccg2_allow_clock_gating(struct dccg *dccg, bool allow);
void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable);
struct dccg *dccg2_create(
struct dc_context *ctx,
const struct dccg_registers *regs,

5
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
View File

@ -1887,8 +1887,9 @@ void dcn10_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

29
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
View File

@ -357,10 +357,26 @@ void dcn20_enable_power_gating_plane(
void dcn20_dccg_init(struct dce_hwseq *hws)
{
struct dc *dc = hws->ctx->dc;
/*
* set MICROSECOND_TIME_BASE_DIV
* 100Mhz refclk -> 0x120264
* 27Mhz refclk -> 0x12021b
* 48Mhz refclk -> 0x120230
*
*/
REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init)
dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg);
/*
* set MILLISECOND_TIME_BASE_DIV
* 100Mhz refclk -> 0x1186a0
* 27Mhz refclk -> 0x106978
* 48Mhz refclk -> 0x10bb80
*
*/
REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
/* This value is dependent on the hardware pipeline delay so set once per SOC */
REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
}
void dcn20_disable_vga(
@ -3140,11 +3156,8 @@ void dcn20_fpga_init_hw(struct dc *dc)
dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2);
if (hws->funcs.dccg_init)
hws->funcs.dccg_init(hws);
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup)
dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg);
if (REG(REFCLK_CNTL))
REG_WRITE(REFCLK_CNTL, 0);
//

5
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
View File

@ -367,8 +367,9 @@ void dcn201_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

9
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
View File

@ -33,7 +33,6 @@
#include "vmid.h"
#include "reg_helper.h"
#include "hw/clk_mgr.h"
#include "hw/dccg.h"
#include "dc_dmub_srv.h"
#include "abm.h"
#include "link_service.h"
@ -88,10 +87,12 @@ int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_
bool dcn21_s0i3_golden_init_wa(struct dc *dc)
{
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done)
return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg);
struct dce_hwseq *hws = dc->hwseq;
uint32_t value = 0;
return false;
value = REG_READ(MICROSECOND_TIME_BASE_DIV);
return value != 0x00120464;
}
void dcn21_exit_optimized_pwr_state(

5
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
View File

@ -801,8 +801,9 @@ void dcn30_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

5
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
View File

@ -247,8 +247,9 @@ void dcn31_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

5
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
View File

@ -963,8 +963,9 @@ void dcn32_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

3
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
View File

@ -286,8 +286,7 @@ void dcn35_init_hw(struct dc *dc)
}
if (dc->debug.disable_mem_low_power) {
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power)
dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false);
REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
}
if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

5
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
View File

@ -326,8 +326,9 @@ void dcn401_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

4
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
View File

@ -224,9 +224,6 @@ struct dccg_funcs {
void (*otg_drop_pixel)(struct dccg *dccg,
uint32_t otg_inst);
void (*dccg_init)(struct dccg *dccg);
void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */
void (*allow_clock_gating)(struct dccg *dccg, bool allow);
void (*enable_memory_low_power)(struct dccg *dccg, bool enable);
void (*set_dpstreamclk_root_clock_gating)(
struct dccg *dccg,
int dp_hpo_inst,
@ -337,7 +334,6 @@ struct dccg_funcs {
void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);
void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);
void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable);
bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg);
};
#endif //__DAL_DCCG_H__