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net: phy: rockchip: optimize for long cable
Change-Id: I125fb3a325946e82ccf021b02df194282b9d60f0 Signed-off-by: Weiguo Hu <hwg@rock-chips.com>
This commit is contained in:
Weiguo Hu
Tao Huang
parent
793ca73b39
commit
623a187bd8
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@ -42,12 +42,38 @@
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#define TSTMODE_ENABLE 0x400
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#define TSTMODE_DISABLE 0x0
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#define DSP_REG_BANK_SEL 0
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#define WOL_REG_BANK_SEL BIT(11)
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#define BIST_REG_BANK_SEL GENMASK(12, 11)
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#define WR_ADDR_A3CFG 0x14
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#define WR_ADDR_A7CFG 0x18
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static int rockchip_init_tstmode(struct phy_device *phydev)
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#define RD_ADDR_A3CFG (0x14 << 5)
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#define RD_ADDR_LPISTA (12 << 5)
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#define A3CFG_100M 0xFC00
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#define A3CFG_TAG 0xFFFF
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#define PHY_ABNORMAL_THRESHOLD 15
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struct rk_int_phy_priv {
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int restore_reg0;
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int restore_a3_config;
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int force_10m_full_mode;
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int a3_config_set;
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int txrx_counters_done_count;
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int last_speed;
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};
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static int rockchip_integrated_phy_init_tstmode(struct phy_device *phydev)
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{
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int ret;
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ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
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if (ret)
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return ret;
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/* Enable access to Analog and DSP register banks */
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ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
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if (ret)
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@ -60,20 +86,15 @@ static int rockchip_init_tstmode(struct phy_device *phydev)
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return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
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}
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static int rockchip_close_tstmode(struct phy_device *phydev)
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{
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/* Back to basic register bank */
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return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
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}
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static int rockchip_integrated_phy_analog_init(struct phy_device *phydev)
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{
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int ret;
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ret = rockchip_init_tstmode(phydev);
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phydev_dbg(phydev, "%s: %d\n", __func__, __LINE__);
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ret = rockchip_integrated_phy_init_tstmode(phydev);
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if (ret)
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return ret;
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/*
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* Adjust tx amplitude to make sginal better,
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* the default value is 0x8.
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@ -85,13 +106,15 @@ static int rockchip_integrated_phy_analog_init(struct phy_device *phydev)
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if (ret)
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return ret;
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return rockchip_close_tstmode(phydev);
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return ret;
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}
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static int rockchip_integrated_phy_config_init(struct phy_device *phydev)
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{
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int val, ret;
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phydev_dbg(phydev, "%s: %d\n", __func__, __LINE__);
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/*
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* The auto MIDX has linked problem on some board,
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* workround to disable auto MDIX.
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@ -107,9 +130,70 @@ static int rockchip_integrated_phy_config_init(struct phy_device *phydev)
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return rockchip_integrated_phy_analog_init(phydev);
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}
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static void rockchip_link_change_notify(struct phy_device *phydev)
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static int rockchip_integrated_phy_probe(struct phy_device *phydev)
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{
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struct rk_int_phy_priv *priv;
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phydev_dbg(phydev, "%s: %d\n", __func__, __LINE__);
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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phydev->priv = priv;
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return 0;
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}
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static void rockchip_integrated_phy_remove(struct phy_device *phydev)
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{
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struct rk_int_phy_priv *priv = phydev->priv;
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phydev_dbg(phydev, "%s: %d\n", __func__, __LINE__);
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kfree(priv);
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}
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static int rockchip_integrated_phy_adjust_a3_config(struct phy_device *phydev,
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int value)
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{
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int ret, val;
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struct rk_int_phy_priv *priv = phydev->priv;
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phydev_dbg(phydev, "%s: %d: value = %x\n", __func__, __LINE__, value);
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if (value == A3CFG_TAG) {
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ret = phy_write(phydev, SMI_ADDR_TSTCNTL,
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TSTCNTL_RD | RD_ADDR_A3CFG);
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if (ret)
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return ret;
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val = phy_read(phydev, SMI_ADDR_TSTREAD1);
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if (val < 0)
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return val;
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priv->restore_a3_config = val;
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priv->a3_config_set = 1;
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ret = phy_write(phydev, SMI_ADDR_TSTWRITE, A3CFG_100M);
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if (ret)
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return ret;
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} else {
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ret = phy_write(phydev, SMI_ADDR_TSTWRITE, value);
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if (ret)
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return ret;
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}
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ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A3CFG);
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if (ret)
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return ret;
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return 0;
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}
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static
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void rockchip_integrated_phy_link_change_notify(struct phy_device *phydev)
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{
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int speed = SPEED_10;
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struct rk_int_phy_priv *priv = phydev->priv;
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if (phydev->autoneg == AUTONEG_ENABLE) {
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int reg = phy_read(phydev, MII_SPECIAL_CONTROL_STATUS);
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@ -142,13 +226,18 @@ static void rockchip_link_change_notify(struct phy_device *phydev)
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* registers are set to default values. So any AFE/DSP
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* registers have to be re-initialized in this case.
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*/
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if ((phydev->speed == SPEED_10) && (speed == SPEED_100)) {
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if (phydev->link &&
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speed == SPEED_100 &&
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priv->last_speed == SPEED_10) {
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int ret = rockchip_integrated_phy_analog_init(phydev);
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if (ret)
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phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n",
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ret);
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}
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if (phydev->link)
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priv->last_speed = speed;
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}
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static int rockchip_set_polarity(struct phy_device *phydev, int polarity)
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@ -185,7 +274,7 @@ static int rockchip_set_polarity(struct phy_device *phydev, int polarity)
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return 0;
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}
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static int rockchip_config_aneg(struct phy_device *phydev)
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static int rockchip_integrated_phy_config_aneg(struct phy_device *phydev)
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{
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int err;
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@ -196,8 +285,145 @@ static int rockchip_config_aneg(struct phy_device *phydev)
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return genphy_config_aneg(phydev);
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}
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static int rockchip_phy_resume(struct phy_device *phydev)
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static int rockchip_integrated_phy_fixup_10M(struct phy_device *phydev)
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{
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int val, ret;
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struct rk_int_phy_priv *priv = phydev->priv;
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/* link partner does not have auto-negotiation ability
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* setting PHY to 10M full-duplex by force
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*/
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if (phydev->state == PHY_RUNNING && !priv->force_10m_full_mode &&
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phydev->link && phydev->speed == SPEED_10) {
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int an_expan;
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val = phy_read(phydev, MII_EXPANSION);
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if (val < 0)
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return val;
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an_expan = val;
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if (!(an_expan & 0x1)) {
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phydev_dbg(phydev, "%s: force_10m_full_mode\n",
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__func__);
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val = phy_read(phydev, MII_BMCR);
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if (val < 0)
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return val;
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priv->restore_reg0 = val;
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val = val & (~BMCR_ANENABLE);
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val &= ~BMCR_SPEED100;
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val |= BMCR_FULLDPLX;
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ret = phy_write(phydev, MII_BMCR, val);
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if (ret)
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return ret;
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priv->force_10m_full_mode = 1;
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}
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/* restore BMCR register */
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} else if (!phydev->link && priv->force_10m_full_mode) {
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phydev_dbg(phydev, "%s: restore force_10m_full_mode\n",
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__func__);
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priv->force_10m_full_mode = 0;
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ret = phy_write(phydev, MII_BMCR, priv->restore_reg0);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int rockchip_integrated_phy_fixup_100M(struct phy_device *phydev)
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{
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int ret, val;
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struct rk_int_phy_priv *priv = phydev->priv;
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/* reset phy when continue detect phy abnormal */
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if (phydev->link && phydev->speed == SPEED_100) {
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/* read wol bank reg12 and check bit 12 */
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ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_RD |
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WOL_REG_BANK_SEL | RD_ADDR_LPISTA);
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if (ret)
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return ret;
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val = phy_read(phydev, SMI_ADDR_TSTREAD1);
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if (val < 0)
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return val;
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if (val & 0x1000)
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priv->txrx_counters_done_count = 0;
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if (!(val & 0x1000))
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priv->txrx_counters_done_count++;
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/* phydev_dbg(phydev, "txrx_counters_done_count = %d,"
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* threshol = %d\n",
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* priv->txrx_counters_done_count,
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* PHY_ABNORMAL_THRESHOLD);
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*/
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if (priv->txrx_counters_done_count >=
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PHY_ABNORMAL_THRESHOLD) {
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phydev_err(phydev, "%s: reset phy\n", __func__);
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priv->txrx_counters_done_count = 0;
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ret = genphy_soft_reset(phydev);
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if (ret < 0)
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return ret;
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}
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} else {
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priv->txrx_counters_done_count = 0;
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}
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/* adjust A3_CONFIG for optimize long cable when 100M link up*/
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if (phydev->link && phydev->speed == SPEED_100 &&
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!priv->a3_config_set) {
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ret = rockchip_integrated_phy_adjust_a3_config
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(phydev,
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A3CFG_TAG);
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if (ret) {
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phydev_err(phydev, "adjust_a3_config fail %x\n",
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A3CFG_TAG);
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return ret;
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}
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/* restore A3_CONFIG when 100M link down */
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} else if (!phydev->link && priv->a3_config_set) {
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priv->a3_config_set = 0;
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ret = rockchip_integrated_phy_adjust_a3_config
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(phydev,
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priv->restore_a3_config);
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if (ret) {
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phydev_err(phydev, "adjust_a3_config fail %x\n",
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priv->restore_a3_config);
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return ret;
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}
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}
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return 0;
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}
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static int rockchip_integrated_phy_read_status(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_read_status(phydev);
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if (ret)
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return ret;
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ret = rockchip_integrated_phy_fixup_10M(phydev);
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if (ret)
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return ret;
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ret = rockchip_integrated_phy_fixup_100M(phydev);
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if (ret)
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return ret;
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return 0;
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}
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static int rockchip_integrated_phy_resume(struct phy_device *phydev)
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{
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struct rk_int_phy_priv *priv = phydev->priv;
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if (phydev->link && phydev->speed == SPEED_100)
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priv->a3_config_set = 0;
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genphy_resume(phydev);
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return rockchip_integrated_phy_config_init(phydev);
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@ -210,13 +436,15 @@ static struct phy_driver rockchip_phy_driver[] = {
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.name = "Rockchip integrated EPHY",
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.features = PHY_BASIC_FEATURES,
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.flags = 0,
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.link_change_notify = rockchip_link_change_notify,
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.probe = rockchip_integrated_phy_probe,
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.remove = rockchip_integrated_phy_remove,
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.link_change_notify = rockchip_integrated_phy_link_change_notify,
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.soft_reset = genphy_soft_reset,
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.config_init = rockchip_integrated_phy_config_init,
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.config_aneg = rockchip_config_aneg,
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.read_status = genphy_read_status,
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.config_aneg = rockchip_integrated_phy_config_aneg,
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.read_status = rockchip_integrated_phy_read_status,
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.suspend = genphy_suspend,
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.resume = rockchip_phy_resume,
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.resume = rockchip_integrated_phy_resume,
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},
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};
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