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arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable PCIe

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Enable the PCIE1 slot available on the RZ/V2N EVK.

Note, the PCIE_REFCLK comes from 5L35023B versa clock generator, once the
support for this clock generator is added, the fixed clock node can be
removed and can be replaced with a reference to the clock generator.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260501105116.33452-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2026-05-01 11:51:16 +01:00 committed by Geert Uytterhoeven
parent 4c443296ff
commit 62169c13d8
1 changed files with 23 additions and 0 deletions
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23
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
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@ -63,6 +63,12 @@ memory@48000000 {
reg = <0x0 0x48000000 0x1 0xf8000000>;
};
pcie_refclk: clock-pcie-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_0p8v: regulator-0p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-0.8V";
@ -333,6 +339,17 @@ &ostm7 {
status = "okay";
};
&pcie {
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
status = "okay";
};
&pcie_port0 {
clocks = <&pcie_refclk>;
clock-names = "ref";
};
&pinctrl {
eth0_pins: eth0 {
pins = "ET0_TXC_TXCLK";
@ -383,6 +400,12 @@ i2c8_pins: i2c8 {
<RZV2N_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
};
pcie_pins: pcie {
pins = "PCIE0_RSTOUTB";
slew-rate = <0>;
renesas,output-impedance = <2>;
};
scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;