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clk: rockchip: px30: Add CLK_SET_RATE_PARENT for clk_i2s0_tx_out_pre

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Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I18e86d31ece992af568fca12c9af2b04f327dd67
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Wyon Bi 2020-05-20 17:35:02 +08:00 committed by Tao Huang
parent 969eda0685
commit 620cc157a7
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-px30.c
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@ -599,7 +599,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
PX30_CLKGATE_CON(9), 14, GFLAGS),
COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0,
COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(28), 14, 2, MFLAGS,
PX30_CLKGATE_CON(9), 15, GFLAGS),
GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT,