ARM: dts: uniphier: add reference clock nodes

Add master clock nodes generated by crystal oscillators.

  PH1-sLD3, PH1-LD4: 24.576 MHz
  PH1-Pro4, ProXstream2: 25.000 MHz
  PH1-Pro5: 20.000 MHz

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arch/arm/boot/dts/uniphier-common32.dtsi

@@ -45,6 +45,13 @@
 /include/ "skeleton.dtsi"
 
 / {
+	clocks {
+		refclk: ref {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+		};
+	};
+
 	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;

arch/arm/boot/dts/uniphier-ph1-ld4.dtsi

@@ -173,6 +173,10 @@ usb2: usb@5a820100 {
 
 };
 
+&refclk {
+	clock-frequency = <24576000>;
+};
+
 &serial3 {
 	interrupts = <0 29 4>;
 };

arch/arm/boot/dts/uniphier-ph1-pro4.dtsi

@@ -195,6 +195,10 @@ usb3: usb@5a810100 {
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-pro4-pinctrl", "syscon";
 };

arch/arm/boot/dts/uniphier-ph1-pro5.dtsi

@@ -189,6 +189,10 @@ i2c6: i2c@58786000 {
 	};
 };
 
+&refclk {
+	clock-frequency = <20000000>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
 };

arch/arm/boot/dts/uniphier-ph1-sld3.dtsi

@@ -68,6 +68,12 @@ cpu@1 {
 	};
 
 	clocks {
+		refclk: ref {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24576000>;
+		};
+
 		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";

arch/arm/boot/dts/uniphier-ph1-sld8.dtsi

@@ -172,6 +172,10 @@ usb2: usb@5a820100 {
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &serial3 {
 	interrupts = <0 29 4>;
 };

arch/arm/boot/dts/uniphier-proxstream2.dtsi

@@ -200,6 +200,10 @@ i2c6: i2c@58786000 {
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &pinctrl {
 	compatible = "socionext,proxstream2-pinctrl", "syscon";
 };