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drm/amd/pm: Use emit_clock_levels in vega20
Move to emit_clock_levels from print_clock_levels Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar
Alex Deucher
parent
0229122fa1
commit
6186199f32
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@ -3362,8 +3362,9 @@ static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
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return link_speed[speed_level];
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}
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static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, char *buf)
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static int vega20_emit_clock_levels(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, char *buf,
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int *offset)
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{
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struct vega20_hwmgr *data =
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(struct vega20_hwmgr *)(hwmgr->backend);
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@ -3375,7 +3376,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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struct pp_clock_levels_with_latency clocks;
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struct vega20_single_dpm_table *fclk_dpm_table =
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&(data->dpm_table.fclk_table);
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int i, now, size = 0;
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int i, now, size = *offset;
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int ret = 0;
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uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
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@ -3387,15 +3388,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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return ret);
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if (vega20_get_sclks(hwmgr, &clocks)) {
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size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
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now / 100);
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size += sysfs_emit_at(buf, size,
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"0: %uMhz * (DPM disabled)\n",
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now / 100);
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break;
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}
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for (i = 0; i < clocks.num_levels; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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i, clocks.data[i].clocks_in_khz / 1000,
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(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
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size += sysfs_emit_at(
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buf, size, "%d: %uMhz %s\n", i,
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clocks.data[i].clocks_in_khz / 1000,
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(clocks.data[i].clocks_in_khz == now * 10) ?
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"*" :
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"");
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break;
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case PP_MCLK:
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@ -3405,15 +3410,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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return ret);
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if (vega20_get_memclocks(hwmgr, &clocks)) {
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size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
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now / 100);
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size += sysfs_emit_at(buf, size,
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"0: %uMhz * (DPM disabled)\n",
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now / 100);
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break;
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}
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for (i = 0; i < clocks.num_levels; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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i, clocks.data[i].clocks_in_khz / 1000,
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(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
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size += sysfs_emit_at(
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buf, size, "%d: %uMhz %s\n", i,
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clocks.data[i].clocks_in_khz / 1000,
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(clocks.data[i].clocks_in_khz == now * 10) ?
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"*" :
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"");
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break;
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case PP_SOCCLK:
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@ -3423,15 +3432,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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return ret);
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if (vega20_get_socclocks(hwmgr, &clocks)) {
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size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
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now / 100);
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size += sysfs_emit_at(buf, size,
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"0: %uMhz * (DPM disabled)\n",
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now / 100);
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break;
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}
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for (i = 0; i < clocks.num_levels; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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i, clocks.data[i].clocks_in_khz / 1000,
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(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
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size += sysfs_emit_at(
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buf, size, "%d: %uMhz %s\n", i,
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clocks.data[i].clocks_in_khz / 1000,
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(clocks.data[i].clocks_in_khz == now * 10) ?
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"*" :
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"");
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break;
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case PP_FCLK:
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@ -3441,9 +3454,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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return ret);
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for (i = 0; i < fclk_dpm_table->count; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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i, fclk_dpm_table->dpm_levels[i].value,
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fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
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size += sysfs_emit_at(
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buf, size, "%d: %uMhz %s\n", i,
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fclk_dpm_table->dpm_levels[i].value,
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fclk_dpm_table->dpm_levels[i].value ==
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(now / 100) ?
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"*" :
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"");
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break;
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case PP_DCEFCLK:
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@ -3453,15 +3470,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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return ret);
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if (vega20_get_dcefclocks(hwmgr, &clocks)) {
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size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
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now / 100);
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size += sysfs_emit_at(buf, size,
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"0: %uMhz * (DPM disabled)\n",
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now / 100);
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break;
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}
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for (i = 0; i < clocks.num_levels; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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i, clocks.data[i].clocks_in_khz / 1000,
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(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
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size += sysfs_emit_at(
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buf, size, "%d: %uMhz %s\n", i,
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clocks.data[i].clocks_in_khz / 1000,
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(clocks.data[i].clocks_in_khz == now * 10) ?
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"*" :
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"");
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break;
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case PP_PCIE:
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@ -3473,40 +3494,45 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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gen_speed = pptable->PcieGenSpeed[i];
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lane_width = pptable->PcieLaneCount[i];
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size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
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(gen_speed == 0) ? "2.5GT/s," :
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(gen_speed == 1) ? "5.0GT/s," :
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(gen_speed == 2) ? "8.0GT/s," :
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(gen_speed == 3) ? "16.0GT/s," : "",
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(lane_width == 1) ? "x1" :
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(lane_width == 2) ? "x2" :
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(lane_width == 3) ? "x4" :
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(lane_width == 4) ? "x8" :
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(lane_width == 5) ? "x12" :
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(lane_width == 6) ? "x16" : "",
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pptable->LclkFreq[i],
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(current_gen_speed == gen_speed) &&
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(current_lane_width == lane_width) ?
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"*" : "");
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size += sysfs_emit_at(
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buf, size, "%d: %s %s %dMhz %s\n", i,
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(gen_speed == 0) ? "2.5GT/s," :
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(gen_speed == 1) ? "5.0GT/s," :
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(gen_speed == 2) ? "8.0GT/s," :
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(gen_speed == 3) ? "16.0GT/s," :
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"",
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(lane_width == 1) ? "x1" :
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(lane_width == 2) ? "x2" :
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(lane_width == 3) ? "x4" :
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(lane_width == 4) ? "x8" :
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(lane_width == 5) ? "x12" :
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(lane_width == 6) ? "x16" :
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"",
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pptable->LclkFreq[i],
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(current_gen_speed == gen_speed) &&
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(current_lane_width ==
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lane_width) ?
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"*" :
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"");
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}
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break;
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case OD_SCLK:
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if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
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size += sprintf(buf + size, "%s:\n", "OD_SCLK");
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size += sprintf(buf + size, "0: %10uMhz\n",
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od_table->GfxclkFmin);
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size += sprintf(buf + size, "1: %10uMhz\n",
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od_table->GfxclkFmax);
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size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
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size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
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od_table->GfxclkFmin);
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size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
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od_table->GfxclkFmax);
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}
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break;
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case OD_MCLK:
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if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
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size += sprintf(buf + size, "%s:\n", "OD_MCLK");
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size += sprintf(buf + size, "1: %10uMhz\n",
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od_table->UclkFmax);
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size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
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size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
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od_table->UclkFmax);
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}
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break;
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@ -3518,32 +3544,38 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
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size += sprintf(buf + size, "%s:\n", "OD_VDDC_CURVE");
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size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
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od_table->GfxclkFreq1,
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od_table->GfxclkVolt1 / VOLTAGE_SCALE);
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size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
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od_table->GfxclkFreq2,
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od_table->GfxclkVolt2 / VOLTAGE_SCALE);
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size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
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od_table->GfxclkFreq3,
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od_table->GfxclkVolt3 / VOLTAGE_SCALE);
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size += sysfs_emit_at(buf, size, "%s:\n",
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"OD_VDDC_CURVE");
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size += sysfs_emit_at(buf, size, "0: %10uMhz %10dmV\n",
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od_table->GfxclkFreq1,
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od_table->GfxclkVolt1 /
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VOLTAGE_SCALE);
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size += sysfs_emit_at(buf, size, "1: %10uMhz %10dmV\n",
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od_table->GfxclkFreq2,
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od_table->GfxclkVolt2 /
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VOLTAGE_SCALE);
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size += sysfs_emit_at(buf, size, "2: %10uMhz %10dmV\n",
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od_table->GfxclkFreq3,
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od_table->GfxclkVolt3 /
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VOLTAGE_SCALE);
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}
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break;
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case OD_RANGE:
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size += sprintf(buf + size, "%s:\n", "OD_RANGE");
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size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
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if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
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size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
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size += sysfs_emit_at(
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buf, size, "SCLK: %7uMhz %10uMhz\n",
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od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
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od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
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}
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if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
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size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
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size += sysfs_emit_at(
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buf, size, "MCLK: %7uMhz %10uMhz\n",
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od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
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od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
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}
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@ -3554,31 +3586,52 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
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size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
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size += sysfs_emit_at(
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buf, size,
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"VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
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od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
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od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
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size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
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size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
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od8_settings[OD8_SETTING_GFXCLK_FREQ1]
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.max_value);
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size += sysfs_emit_at(
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buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1]
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.min_value,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1]
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.max_value);
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size += sysfs_emit_at(
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buf, size,
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"VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
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od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
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od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
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size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
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size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
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od8_settings[OD8_SETTING_GFXCLK_FREQ2]
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.max_value);
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size += sysfs_emit_at(
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buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2]
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.min_value,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2]
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.max_value);
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size += sysfs_emit_at(
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buf, size,
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"VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
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od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
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od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
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size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
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od8_settings[OD8_SETTING_GFXCLK_FREQ3]
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.max_value);
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size += sysfs_emit_at(
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buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3]
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.min_value,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3]
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.max_value);
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}
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break;
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default:
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break;
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}
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return size;
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*offset = size;
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return 0;
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}
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static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
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@ -4412,7 +4465,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
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.odn_edit_dpm_table = vega20_odn_edit_dpm_table,
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/* for sysfs to retrive/set gfxclk/memclk */
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.force_clock_level = vega20_force_clock_level,
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.print_clock_levels = vega20_print_clock_levels,
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.emit_clock_levels = vega20_emit_clock_levels,
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.read_sensor = vega20_read_sensor,
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.get_ppfeature_status = vega20_get_ppfeature_status,
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.set_ppfeature_status = vega20_set_ppfeature_status,
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