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Merge branch 'bnxt_en-bug-fixes'
Michael Chan says: ==================== bnxt_en: Bug fixes This series include 3 bug fixes: 1. queue start bug fix on the VNIC's default ring. 2 refactoring patches preceed the actual bug fix. 2. Bug fix for TPA data corruption seen on some ARM systems. 3. PTP PPS setting bug fix. ==================== Link: https://patch.msgid.link/20260731190937.807270-1-michael.chan@broadcom.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
6183a645aa
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@ -4611,11 +4611,14 @@ static void bnxt_init_one_rx_agg_ring_rxbd(struct bnxt *bp,
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type = ((u32)rxr->rx_page_size << RX_BD_LEN_SHIFT) |
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RX_BD_TYPE_RX_AGG_BD;
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/* On P7, setting EOP will cause the chip to disable
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* Relaxed Ordering (RO) for TPA data. Disable EOP for
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* potentially higher performance with RO.
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/* Disable EOP if TPA is enabled to prevent overlapping zero
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* padding with the next segment's data. On P7_PLUS, EOP will
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* automatically disable Relaxed Ordering (RO) to prevent
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* potential data corruption (and may degrade performance). On
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* older chips, RO will not be automatically disabled and may
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* cause corruption.
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*/
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if (BNXT_CHIP_P5_AND_MINUS(bp) || !(bp->flags & BNXT_FLAG_TPA))
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if (!(bp->flags & BNXT_FLAG_TPA))
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type |= RX_BD_FLAGS_AGG_EOP;
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bnxt_init_rxbd_pages(ring, type);
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@ -6704,22 +6707,36 @@ int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
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static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
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{
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bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
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u16 i, j;
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u16 i, j, min_j = bp->rx_nr_rings - 1;
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if (!vnic->rss_table)
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goto skip_rss_tbl;
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/* Fill the RSS indirection table with ring group ids */
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for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
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if (!no_rss)
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j = bp->rss_indir_tbl[i];
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min_j = min(j, min_j);
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vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
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}
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skip_rss_tbl:
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if (vnic->rss_table && !no_rss)
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vnic->default_rx_ring = min_j;
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else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
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vnic->default_rx_ring = vnic->vnic_id - 1;
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else if ((vnic->vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
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vnic->default_rx_ring = bp->rx_nr_rings - 1;
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else
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vnic->default_rx_ring = 0;
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}
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static void bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
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struct bnxt_vnic_info *vnic)
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{
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u16 tbl_size, i, min_j = bp->rx_nr_rings - 1;
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__le16 *ring_tbl = vnic->rss_table;
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struct bnxt_rx_ring_info *rxr;
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u16 tbl_size, i;
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tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
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@ -6732,6 +6749,7 @@ static void bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
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j = ethtool_rxfh_context_indir(vnic->rss_ctx)[i];
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else
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j = bp->rss_indir_tbl[i];
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min_j = min(j, min_j);
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rxr = &bp->rx_ring[j];
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ring_id = rxr->rx_ring_struct.fw_ring_id;
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@ -6739,19 +6757,15 @@ static void bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
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ring_id = bnxt_cp_ring_for_rx(bp, rxr);
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*ring_tbl++ = cpu_to_le16(ring_id);
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}
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vnic->default_rx_ring = min_j;
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}
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static void
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__bnxt_hwrm_vnic_set_rss(struct bnxt *bp, struct hwrm_vnic_rss_cfg_input *req,
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struct bnxt_vnic_info *vnic)
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{
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if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
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bnxt_fill_hw_rss_tbl_p5(bp, vnic);
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if (bp->flags & BNXT_FLAG_CHIP_P7)
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req->flags |= VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT;
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} else {
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bnxt_fill_hw_rss_tbl(bp, vnic);
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}
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if (bp->flags & BNXT_FLAG_CHIP_P7)
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req->flags |= VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT;
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if (bp->rss_hash_delta) {
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req->hash_type = cpu_to_le32(bp->rss_hash_delta);
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@ -6803,6 +6817,7 @@ static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp,
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if (!set_rss)
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return hwrm_req_send(bp, req);
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bnxt_fill_hw_rss_tbl_p5(bp, vnic);
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__bnxt_hwrm_vnic_set_rss(bp, req, vnic);
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ring_tbl_map = vnic->rss_table_dma_addr;
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nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
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@ -6939,8 +6954,9 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
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return rc;
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if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
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struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
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struct bnxt_rx_ring_info *rxr;
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rxr = &bp->rx_ring[vnic->default_rx_ring];
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req->default_rx_ring_id =
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cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
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req->default_cmpl_ring_id =
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@ -6973,13 +6989,7 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
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req->cos_rule = cpu_to_le16(0xffff);
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}
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if (vnic->flags & BNXT_VNIC_RSS_FLAG)
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ring = 0;
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else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
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ring = vnic->vnic_id - 1;
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else if ((vnic->vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
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ring = bp->rx_nr_rings - 1;
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ring = vnic->default_rx_ring;
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grp_idx = bp->rx_ring[ring].bnapi->index;
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req->dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
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req->lb_rule = cpu_to_le16(0xffff);
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@ -10866,6 +10876,7 @@ static int __bnxt_setup_vnic(struct bnxt *bp, struct bnxt_vnic_info *vnic)
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}
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skip_rss_ctx:
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bnxt_fill_hw_rss_tbl(bp, vnic);
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/* configure default vnic, ring grp */
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rc = bnxt_hwrm_vnic_cfg(bp, vnic);
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if (rc) {
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@ -11090,6 +11101,11 @@ static int bnxt_set_vnic_mru_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic,
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vnic->vnic_id, rc);
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return rc;
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}
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if (rxr_id == vnic->default_rx_ring) {
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rc = bnxt_hwrm_vnic_cfg(bp, vnic);
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if (rc)
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return rc;
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}
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}
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vnic->mru = mru;
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bnxt_hwrm_vnic_update(bp, vnic,
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@ -11171,6 +11187,9 @@ static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
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return rc;
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}
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/* Setup the proper default RX ring */
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bnxt_fill_hw_rss_tbl(bp, vnic);
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rc = bnxt_hwrm_vnic_cfg(bp, vnic);
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if (rc) {
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netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
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@ -1334,6 +1334,7 @@ struct bnxt_vnic_info {
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#define BNXT_VNIC_RSSCTX_FLAG 0x40
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struct ethtool_rxfh_context *rss_ctx;
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u32 vnic_id;
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u16 default_rx_ring;
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};
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struct bnxt_rss_ctx {
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@ -495,12 +495,15 @@ static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info,
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return rc;
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case PTP_CLK_REQ_PPS:
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/* Configure PHC PPS IN */
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rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN);
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pin_id = 0;
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if (!on)
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break;
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rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN);
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if (rc)
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return rc;
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rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL);
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if (!rc)
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ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL;
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ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_INTERNAL;
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return rc;
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default:
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netdev_err(ptp->bp->dev, "Unrecognized PIN function\n");
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