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drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D
Xe3p_LPD has the same behavior as for Xe3_LPD with respect to DMC context data for pipes C and D, which are lost when their power wells are disabled. As such, let's extend the condition for Xe3_LPD in need_pipedmc_load_mmio() to also catch Xe3p_LPD. Bspec: 68851 Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-13-00e87b510ae7@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
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@ -718,11 +718,11 @@ static bool need_pipedmc_load_program(struct intel_display *display)
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static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)
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{
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/*
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* PTL:
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* Xe3_LPD/Xe3p_LPD:
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* - pipe A/B DMC doesn't need save/restore
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* - pipe C/D DMC is in PG0, needs manual save/restore
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*/
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if (DISPLAY_VER(display) == 30)
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if (IS_DISPLAY_VER(display, 30, 35))
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return pipe >= PIPE_C;
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/*
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