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riscv: dts: sophgo: cv18xx: Add RTCSYS device node

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Add the RTCSYS MFD node: in Cvitek CV18xx and its successors RTC Subsystem
is quite advanced and provides SoC power management functions as well.

The SoC family also contains DW8051 block (Intel 8051 compatible CPU core)
and an associated SRAM. The corresponding control registers are mapped into
RTCSYS address space as well.

Link: https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250513203128.620731-1-alexander.sverdlin@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
This commit is contained in:
Alexander Sverdlin 2025-05-13 22:31:25 +02:00 committed by Inochi Amaoto
parent 19272b37aa
commit 616c84f047
1 changed files with 12 additions and 0 deletions
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12
arch/riscv/boot/dts/sophgo/cv180x.dtsi
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@ -307,5 +307,17 @@ dmac: dma-controller@4330000 {
snps,data-width = <2>;
status = "disabled";
};
rtc@5025000 {
compatible = "sophgo,cv1800b-rtc", "syscon";
reg = <0x5025000 0x2000>;
interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "longpress", "vbat";
clocks = <&clk CLK_RTC_25M>,
<&clk CLK_SRC_RTC_SYS_0>;
clock-names = "rtc", "mcu";
};
};
};