Merge branches 'acpi-processor', 'acpi-cppc' and 'acpi-pci'

Merge an ACPI processor driver update, two ACPI CPPC library updates
and ACPI PCI/CXL support updates for 7.2-rc1:

 - Add cpuidle driver check in acpi_processor_register_idle_driver() to
   avoid evaluating _CST unnecessarily (Tony W Wang-oc)

 - Suppress UBSAN warning caused by field misuse during PCC-based
   register access in the ACPI CPPC library (Jeremy Linton)

 - Add support for CPPC v4 to the ACPI CPPC library (Sumit Gupta)

 - Update the ACPI device enumeration code to honor _DEP for ACPI0016
   PCI/CXL host bridges and make the ACPI PCI root driver clear _DEP
   dependencies for PCI roots that have become operational (Chen Pei)

* acpi-processor:
  ACPI: processor: Add cpuidle driver check in acpi_processor_register_idle_driver()

* acpi-cppc:
  ACPI: CPPC: Suppress UBSAN warning caused by field misuse
  ACPI: CPPC: Add support for CPPC v4

* acpi-pci:
  ACPI: scan: Honor _DEP for ACPI0016 PCI/CXL host bridge
  ACPI: PCI: Clear _DEP dependencies after PCI root bridge attach
This commit is contained in:
Rafael J. Wysocki 2026-06-11 15:34:30 +02:00
commit 615f90d3b1
5 changed files with 44 additions and 12 deletions

View File

@ -134,7 +134,7 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
* cpc_regs[] with the corresponding index. 0 means mandatory and 1
* means optional.
*/
#define REG_OPTIONAL (0x1FC7D0)
#define REG_OPTIONAL (0x7FC7D0)
/*
* Use the index of the register in per-cpu cpc_regs[] to check if
@ -185,8 +185,13 @@ show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
/* Check for valid access_width, otherwise, fallback to using bit_width */
#define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
/*
* PCC reuses the access_width field as the subspace id, so only decode access
* size for non-PCC registers. Otherwise, use the bit_width.
*/
#define GET_BIT_WIDTH(reg) (((reg)->access_width && \
(reg)->space_id != ACPI_ADR_SPACE_PLATFORM_COMM) ? \
(8 << ((reg)->access_width - 1)) : (reg)->bit_width)
/* Shift and apply the mask for CPC reads/writes */
#define MASK_VAL_READ(reg, val) (((val) >> (reg)->bit_offset) & \
@ -751,18 +756,19 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
/*
* Disregard _CPC if the number of entries in the return package is not
* as expected, but support future revisions being proper supersets of
* the v3 and only causing more entries to be returned by _CPC.
* the v4 and only causing more entries to be returned by _CPC.
*/
if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
(cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
(cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
(cpc_rev == CPPC_V4_REV && num_ent != CPPC_V4_NUM_ENT) ||
(cpc_rev > CPPC_V4_REV && num_ent <= CPPC_V4_NUM_ENT)) {
pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
num_ent, pr->id);
goto out_free;
}
if (cpc_rev > CPPC_V3_REV) {
num_ent = CPPC_V3_NUM_ENT;
cpc_rev = CPPC_V3_REV;
if (cpc_rev > CPPC_V4_REV) {
num_ent = CPPC_V4_NUM_ENT;
cpc_rev = CPPC_V4_REV;
}
cpc_ptr->num_entries = num_ent;
@ -845,6 +851,16 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
} else if (cpc_obj->type == ACPI_TYPE_PACKAGE && (i - 2) == RESOURCE_PRIORITY) {
/*
* ACPI 6.6, s8.4.6.1.2.7 defines Resource Priority as a
* Package of Resource Priority Register Descriptor sub-packages.
* Parsing the full structure is not yet supported.
* Mark the register as unsupported for now.
*/
pr_debug("CPU:%d Resource Priority not supported\n", pr->id);
cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = 0;
} else {
pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
i, pr->id);
@ -1045,7 +1061,6 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
* by the bit width field; the access size is used to indicate
* the PCC subspace id.
*/
size = reg->bit_width;
vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
}
else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
@ -1118,7 +1133,6 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
* by the bit width field; the access size is used to indicate
* the PCC subspace id.
*/
size = reg->bit_width;
vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
}
else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)

View File

@ -755,6 +755,10 @@ static int acpi_pci_root_add(struct acpi_device *device,
pci_lock_rescan_remove();
pci_bus_add_devices(root->bus);
pci_unlock_rescan_remove();
/* Clear _DEP dependencies to allow consumers to enumerate */
acpi_dev_clear_dependencies(device);
return 1;
remove_dmar:

View File

@ -1355,6 +1355,15 @@ void acpi_processor_register_idle_driver(void)
int ret = -ENODEV;
int cpu;
/*
* If a cpuidle driver is already registered, there is no need to
* evaluate _CST or attempt to register the ACPI idle driver.
*/
if (cpuidle_get_driver()) {
pr_debug("cpuidle driver %pS already registered.\n", cpuidle_get_driver());
return;
}
acpi_processor_update_max_cstate();
/*

View File

@ -867,6 +867,7 @@ static const char * const acpi_honor_dep_ids[] = {
"RSCV0005", /* RISC-V SBI MPXY MBOX */
"RSCV0006", /* RISC-V RPMI SYSMSI */
"PNP0C0F", /* PCI Link Device */
"ACPI0016", /* CXL/PCIe host bridge: CXL root (ACPI0017) depends on PCI root attach */
NULL
};

View File

@ -17,16 +17,18 @@
#include <acpi/pcc.h>
#include <acpi/processor.h>
/* CPPCv2 and CPPCv3 support */
/* CPPCv2, CPPCv3 and CPPCv4 support */
#define CPPC_V2_REV 2
#define CPPC_V3_REV 3
#define CPPC_V4_REV 4
#define CPPC_V2_NUM_ENT 21
#define CPPC_V3_NUM_ENT 23
#define CPPC_V4_NUM_ENT 25
#define PCC_CMD_COMPLETE_MASK (1 << 0)
#define PCC_ERROR_MASK (1 << 2)
#define MAX_CPC_REG_ENT 21
#define MAX_CPC_REG_ENT 23
/* CPPC specific PCC commands. */
#define CMD_READ 0
@ -109,6 +111,8 @@ enum cppc_regs {
REFERENCE_PERF,
LOWEST_FREQ,
NOMINAL_FREQ,
OSPM_NOMINAL_PERF,
RESOURCE_PRIORITY,
};
/*