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drm/xe: Drop __engine_mask

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Not really used, it's just a copy of engine_mask, which already reads
the fuses to mark engines as available/not-available.

Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513213751.1017791-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
Lucas De Marchi 2024-05-13 14:37:47 -07:00
parent 664de50cbf
commit 61549a2ee5
4 changed files with 5 additions and 14 deletions
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3
drivers/gpu/drm/xe/xe_gt.c
View File

@ -518,9 +518,6 @@ int xe_gt_init_hwconfig(struct xe_gt *gt)
if (err) if (err)
goto out_fw; goto out_fw;
/* XXX: Fake that we pull the engine mask from hwconfig blob */
gt->info.engine_mask = gt->info.__engine_mask;
out_fw: out_fw:
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
out: out:

6
drivers/gpu/drm/xe/xe_gt_types.h
View File

@ -114,12 +114,6 @@ struct xe_gt {
u32 reference_clock; u32 reference_clock;
/** @info.engine_mask: mask of engines present on GT */ /** @info.engine_mask: mask of engines present on GT */
u64 engine_mask; u64 engine_mask;
/**
* @info.__engine_mask: mask of engines present on GT read from
* xe_pci.c, used to fake reading the engine_mask from the
* hwconfig blob.
*/
u64 __engine_mask;
/** @info.gmdid: raw GMD_ID value from hardware */ /** @info.gmdid: raw GMD_ID value from hardware */
u32 gmdid; u32 gmdid;
/** @info.id: Unique ID of this GT within the PCI Device */ /** @info.id: Unique ID of this GT within the PCI Device */

4
drivers/gpu/drm/xe/xe_migrate.c
View File

@ -936,8 +936,8 @@ static bool has_service_copy_support(struct xe_gt *gt)
* all of the actual service copy engines (BCS1-BCS8) have been fused * all of the actual service copy engines (BCS1-BCS8) have been fused
* off. * off.
*/ */
return gt->info.__engine_mask & GENMASK(XE_HW_ENGINE_BCS8, return gt->info.engine_mask & GENMASK(XE_HW_ENGINE_BCS8,
XE_HW_ENGINE_BCS1); XE_HW_ENGINE_BCS1);
} }
static u32 emit_clear_cmd_len(struct xe_gt *gt) static u32 emit_clear_cmd_len(struct xe_gt *gt)

6
drivers/gpu/drm/xe/xe_pci.c
View File

@ -663,9 +663,9 @@ static int xe_info_init(struct xe_device *xe,
gt->info.id = xe->info.gt_count++; gt->info.id = xe->info.gt_count++;
gt->info.type = XE_GT_TYPE_MAIN; gt->info.type = XE_GT_TYPE_MAIN;
gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
gt->info.__engine_mask = graphics_desc->hw_engine_mask; gt->info.engine_mask = graphics_desc->hw_engine_mask;
if (MEDIA_VER(xe) < 13 && media_desc) if (MEDIA_VER(xe) < 13 && media_desc)
gt->info.__engine_mask |= media_desc->hw_engine_mask; gt->info.engine_mask |= media_desc->hw_engine_mask;
if (MEDIA_VER(xe) < 13 || !media_desc) if (MEDIA_VER(xe) < 13 || !media_desc)
continue; continue;
@ -681,7 +681,7 @@ static int xe_info_init(struct xe_device *xe,
gt = tile->media_gt; gt = tile->media_gt;
gt->info.type = XE_GT_TYPE_MEDIA; gt->info.type = XE_GT_TYPE_MEDIA;
gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
gt->info.__engine_mask = media_desc->hw_engine_mask; gt->info.engine_mask = media_desc->hw_engine_mask;
gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET; gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET;
gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH; gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH;