drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)

Despite having different IP offsets the computed address of the register(s)
are the same between gfx7..gfx10.  This patch fixes the offset relative
to the GC block on gfx10.

(v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ...

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tom St Denis 2020-06-16 08:47:04 -04:00 committed by Alex Deucher
parent 9fb1067101
commit 614c56111c
2 changed files with 4 additions and 4 deletions

View File

@ -21,9 +21,9 @@
#ifndef _gc_10_1_0_OFFSET_HEADER
#define _gc_10_1_0_OFFSET_HEADER
#define mmSQ_DEBUG_STS_GLOBAL 0x0309
#define mmSQ_DEBUG_STS_GLOBAL 0x10A9
#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
#define mmSQ_DEBUG_STS_GLOBAL2 0x10B0
#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
// addressBlock: gc_sdma0_sdma0dec

View File

@ -22,9 +22,9 @@
#ifndef _gc_10_3_0_OFFSET_HEADER
#define _gc_10_3_0_OFFSET_HEADER
#define mmSQ_DEBUG_STS_GLOBAL 0x0309
#define mmSQ_DEBUG_STS_GLOBAL 0x10A9
#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
#define mmSQ_DEBUG_STS_GLOBAL2 0x10B0
#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
// addressBlock: gc_sdma0_sdma0dec