github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-31 10:33:41 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/i915/vdsc: Add a check for dsc split cases

Browse Source 
In intel_vdsc_get_config we only read the primary dsc engine register
and not take into account if the other dsc engine is in use and if
both registers have the same value or not this patche fixes that by
adding a check.

--v3
-Remove superfluos new line [Jani]
-Fix register naming [Jani]

--v5
-pps_temp0/pps_temp1 can be assigned where they are used [Ankit]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-3-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal 2023-08-28 11:12:55 +05:30 committed by Animesh Manna
parent 76342fce58
commit 611977c3e4
1 changed files with 13 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@ -1002,7 +1002,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1;
if (!intel_dsc_source_support(crtc_state))
return;
@ -1028,11 +1028,23 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
/* PPS0 & PPS1 */
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
if (crtc_state->dsc.dsc_split) {
pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
}
} else {
pps0 = intel_de_read(dev_priv,
ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
pps1 = intel_de_read(dev_priv,
ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
if (crtc_state->dsc.dsc_split) {
pps_temp0 = intel_de_read(dev_priv,
ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
pps_temp1 = intel_de_read(dev_priv,
ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
}
}
vdsc_cfg->bits_per_pixel = pps1;