mirror of
https://github.com/torvalds/linux.git
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net: airoha: fix BQL underflow in shared QDMA TX ring
When multiple netdevs share a QDMA TX ring and one device is stopped,
netdev_tx_reset_subqueue() zeroes that device's BQL counters while its
pending skbs remain in the shared HW TX ring. When NAPI later completes
those skbs via netdev_tx_completed_queue(), the already-zeroed
dql->num_queued counter underflows.
Fix the issue:
- Remove netdev_tx_reset_subqueue() from airoha_dev_stop() so pending
skbs are completed naturally by NAPI with proper BQL accounting.
- Rework airoha_qdma_tx_cleanup() to disable TX DMA, flush BQL
counters, DMA-unmap and free all pending skbs while skb->dev
references are still valid. Use a per-queue flushing flag checked
under q->lock in airoha_dev_xmit() to prevent races between teardown
and transmit. Call airoha_qdma_stop_napi() before
airoha_qdma_tx_cleanup() at the call sites.
- Move DMA engine start into probe. Split DMA teardown so TX DMA is
disabled in airoha_qdma_tx_cleanup() and RX DMA in
airoha_qdma_cleanup().
- Remove qdma->users counter since DMA lifetime is now tied to
probe/cleanup rather than per-netdev open/stop.
Fixes: a9c2ca61fe ("net: airoha: Support multiple net_devices for a single FE GDM port")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20260620-airoha-bql-fixes-v3-1-76b95374e63e@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Lorenzo Bianconi
Jakub Kicinski
parent
510a283f4d
commit
6117098309
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@ -1004,6 +1004,7 @@ static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget)
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e = &q->entry[index];
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skb = e->skb;
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e->skb = NULL;
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dma_unmap_single(eth->dev, e->dma_addr, e->dma_len,
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DMA_TO_DEVICE);
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@ -1147,55 +1148,76 @@ static int airoha_qdma_init_tx(struct airoha_qdma *qdma)
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return 0;
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}
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static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
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static void airoha_qdma_tx_cleanup(struct airoha_qdma *qdma)
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{
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struct airoha_qdma *qdma = q->qdma;
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struct airoha_eth *eth = qdma->eth;
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int i, qid = q - &qdma->q_tx[0];
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u16 index = 0;
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u32 status;
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int i;
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spin_lock_bh(&q->lock);
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for (i = 0; i < q->ndesc; i++) {
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struct airoha_queue_entry *e = &q->entry[i];
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struct airoha_qdma_desc *desc = &q->desc[i];
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airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
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GLOBAL_CFG_TX_DMA_EN_MASK);
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if (read_poll_timeout(airoha_qdma_rr, status,
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!(status & GLOBAL_CFG_TX_DMA_BUSY_MASK),
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USEC_PER_MSEC, 50 * USEC_PER_MSEC, true,
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qdma, REG_QDMA_GLOBAL_CFG))
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dev_warn(qdma->eth->dev, "QDMA TX DMA busy timeout\n");
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if (!e->dma_addr)
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for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
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struct airoha_queue *q = &qdma->q_tx[i];
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u16 index = 0;
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int j;
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if (!q->ndesc)
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continue;
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dma_unmap_single(eth->dev, e->dma_addr, e->dma_len,
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DMA_TO_DEVICE);
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dev_kfree_skb_any(e->skb);
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e->dma_addr = 0;
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e->skb = NULL;
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list_add_tail(&e->list, &q->tx_list);
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spin_lock_bh(&q->lock);
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/* Reset DMA descriptor */
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WRITE_ONCE(desc->ctrl, 0);
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WRITE_ONCE(desc->addr, 0);
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WRITE_ONCE(desc->data, 0);
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WRITE_ONCE(desc->msg0, 0);
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WRITE_ONCE(desc->msg1, 0);
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WRITE_ONCE(desc->msg2, 0);
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q->flushing = true;
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for (j = 0; j < q->ndesc; j++) {
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struct airoha_queue_entry *e = &q->entry[j];
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struct airoha_qdma_desc *desc = &q->desc[j];
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struct sk_buff *skb = e->skb;
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q->queued--;
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if (!e->dma_addr)
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continue;
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dma_unmap_single(qdma->eth->dev, e->dma_addr,
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e->dma_len, DMA_TO_DEVICE);
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e->dma_addr = 0;
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list_add_tail(&e->list, &q->tx_list);
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WRITE_ONCE(desc->ctrl, 0);
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WRITE_ONCE(desc->addr, 0);
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WRITE_ONCE(desc->data, 0);
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WRITE_ONCE(desc->msg0, 0);
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WRITE_ONCE(desc->msg1, 0);
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WRITE_ONCE(desc->msg2, 0);
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if (skb) {
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struct netdev_queue *txq;
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txq = skb_get_tx_queue(skb->dev, skb);
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netdev_tx_completed_queue(txq, 1, skb->len);
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dev_kfree_skb_any(skb);
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e->skb = NULL;
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}
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q->queued--;
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}
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if (!list_empty(&q->tx_list)) {
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struct airoha_queue_entry *e;
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e = list_first_entry(&q->tx_list,
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struct airoha_queue_entry, list);
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index = e - q->entry;
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}
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airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(i), TX_RING_CPU_IDX_MASK,
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FIELD_PREP(TX_RING_CPU_IDX_MASK, index));
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airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(i), TX_RING_DMA_IDX_MASK,
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FIELD_PREP(TX_RING_DMA_IDX_MASK, index));
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spin_unlock_bh(&q->lock);
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}
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if (!list_empty(&q->tx_list)) {
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struct airoha_queue_entry *e;
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e = list_first_entry(&q->tx_list, struct airoha_queue_entry,
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list);
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index = e - q->entry;
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}
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/* Set TX_DMA_IDX to TX_CPU_IDX to notify the hw the QDMA TX ring is
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* empty.
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*/
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airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
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FIELD_PREP(TX_RING_CPU_IDX_MASK, index));
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airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK,
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FIELD_PREP(TX_RING_DMA_IDX_MASK, index));
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spin_unlock_bh(&q->lock);
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}
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static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
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@ -1523,10 +1545,23 @@ static int airoha_qdma_init(struct platform_device *pdev,
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return airoha_qdma_hw_init(qdma);
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}
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static void airoha_qdma_cleanup(struct airoha_qdma *qdma)
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static void airoha_qdma_cleanup(struct airoha_eth *eth,
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struct airoha_qdma *qdma)
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{
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int i;
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if (test_bit(DEV_STATE_INITIALIZED, ð->state)) {
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u32 status;
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airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
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GLOBAL_CFG_RX_DMA_EN_MASK);
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if (read_poll_timeout(airoha_qdma_rr, status,
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!(status & GLOBAL_CFG_RX_DMA_BUSY_MASK),
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USEC_PER_MSEC, 50 * USEC_PER_MSEC, true,
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qdma, REG_QDMA_GLOBAL_CFG))
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dev_warn(eth->dev, "QDMA RX DMA busy timeout\n");
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}
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for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
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if (!qdma->q_rx[i].ndesc)
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continue;
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@ -1546,12 +1581,6 @@ static void airoha_qdma_cleanup(struct airoha_qdma *qdma)
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netif_napi_del(&qdma->q_tx_irq[i].napi);
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}
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for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
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if (!qdma->q_tx[i].ndesc)
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continue;
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airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
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}
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}
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static int airoha_hw_init(struct platform_device *pdev,
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@ -1593,7 +1622,7 @@ static int airoha_hw_init(struct platform_device *pdev,
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return 0;
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error:
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for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
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airoha_qdma_cleanup(ð->qdma[i]);
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airoha_qdma_cleanup(eth, ð->qdma[i]);
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return err;
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}
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@ -1603,7 +1632,7 @@ static void airoha_hw_cleanup(struct airoha_eth *eth)
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int i;
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for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
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airoha_qdma_cleanup(ð->qdma[i]);
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airoha_qdma_cleanup(eth, ð->qdma[i]);
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airoha_ppe_deinit(eth);
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}
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@ -1837,11 +1866,6 @@ static int airoha_dev_open(struct net_device *netdev)
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}
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port->users++;
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airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
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GLOBAL_CFG_TX_DMA_EN_MASK |
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GLOBAL_CFG_RX_DMA_EN_MASK);
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qdma->users++;
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if (!airoha_is_lan_gdm_dev(dev) &&
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airoha_ppe_is_enabled(qdma->eth, 1))
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pse_port = FE_PSE_PORT_PPE2;
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@ -1880,12 +1904,9 @@ static int airoha_dev_stop(struct net_device *netdev)
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struct airoha_gdm_dev *dev = netdev_priv(netdev);
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struct airoha_gdm_port *port = dev->port;
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struct airoha_qdma *qdma = dev->qdma;
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int i;
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netif_tx_disable(netdev);
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airoha_set_vip_for_gdm_port(dev, false);
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for (i = 0; i < netdev->num_tx_queues; i++)
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netdev_tx_reset_subqueue(netdev, i);
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if (--port->users)
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airoha_set_port_mtu(dev->eth, port);
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@ -1893,20 +1914,6 @@ static int airoha_dev_stop(struct net_device *netdev)
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airoha_set_gdm_port_fwd_cfg(qdma->eth,
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REG_GDM_FWD_CFG(port->id),
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FE_PSE_PORT_DROP);
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if (!--qdma->users) {
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airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
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GLOBAL_CFG_TX_DMA_EN_MASK |
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GLOBAL_CFG_RX_DMA_EN_MASK);
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for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
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if (!qdma->q_tx[i].ndesc)
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continue;
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airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
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}
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}
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return 0;
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}
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@ -2229,6 +2236,9 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
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spin_lock_bh(&q->lock);
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if (q->flushing)
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goto error_unlock;
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txq = skb_get_tx_queue(netdev, skb);
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nr_frags = 1 + skb_shinfo(skb)->nr_frags;
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@ -2309,7 +2319,7 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
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e->dma_addr = 0;
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}
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list_splice(&tx_list, &q->tx_list);
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error_unlock:
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spin_unlock_bh(&q->lock);
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error:
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dev_kfree_skb_any(skb);
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@ -3420,8 +3430,12 @@ static int airoha_probe(struct platform_device *pdev)
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if (err)
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goto error_netdev_free;
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for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
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for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
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airoha_qdma_start_napi(ð->qdma[i]);
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airoha_qdma_set(ð->qdma[i], REG_QDMA_GLOBAL_CFG,
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GLOBAL_CFG_TX_DMA_EN_MASK |
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GLOBAL_CFG_RX_DMA_EN_MASK);
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}
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for_each_child_of_node(pdev->dev.of_node, np) {
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if (!of_device_is_compatible(np, "airoha,eth-mac"))
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@ -3444,8 +3458,10 @@ static int airoha_probe(struct platform_device *pdev)
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return 0;
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error_napi_stop:
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for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
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for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
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airoha_qdma_stop_napi(ð->qdma[i]);
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airoha_qdma_tx_cleanup(ð->qdma[i]);
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}
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for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
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struct airoha_gdm_port *port = eth->ports[i];
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@ -3481,8 +3497,10 @@ static void airoha_remove(struct platform_device *pdev)
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struct airoha_eth *eth = platform_get_drvdata(pdev);
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int i;
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for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
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for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
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airoha_qdma_stop_napi(ð->qdma[i]);
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airoha_qdma_tx_cleanup(ð->qdma[i]);
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}
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for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
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struct airoha_gdm_port *port = eth->ports[i];
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@ -197,6 +197,7 @@ struct airoha_queue {
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int free_thr;
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int buf_size;
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bool txq_stopped;
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bool flushing;
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struct napi_struct napi;
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struct page_pool *page_pool;
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@ -524,8 +525,6 @@ struct airoha_qdma {
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struct airoha_eth *eth;
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void __iomem *regs;
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int users;
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struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS];
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struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ];
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