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wifi: ath12k: Move HTT Tx specific code to newly introduced files
WLAN Host driver interacts with the Firmware and vice versa using Host-To-Target (HTT) interface. Relocate HTT specific code from dp_tx.c to dp_htt.c introduced for HTT interface. These code is compiled as part of the common module ath12k.ko. Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.4.1-00199-QCAHKSWPL_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3 Signed-off-by: Harsh Kumar Bijlani <quic_hbijlani@quicinc.com> Signed-off-by: Ripan Deuri <quic_rdeuri@quicinc.com> Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com> Reviewed-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Link: https://patch.msgid.link/20250828173553.3341351-20-quic_rdeuri@quicinc.com Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
This commit is contained in:
parent
71a3f92c51
commit
611297ee9f
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@ -441,8 +441,6 @@ void ath12k_dp_partner_cc_init(struct ath12k_base *ab);
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int ath12k_dp_pdev_alloc(struct ath12k_base *ab);
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void ath12k_dp_pdev_pre_alloc(struct ath12k *ar);
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void ath12k_dp_pdev_free(struct ath12k_base *ab);
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int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
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int mac_id, enum hal_ring_type ring_type);
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int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr);
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void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr);
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void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring);
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@ -9,6 +9,7 @@
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#include "htc.h"
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#include "dp_htt.h"
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#include "debugfs_htt_stats.h"
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#include "debugfs.h"
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static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
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u16 peer_id)
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@ -642,3 +643,685 @@ void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab,
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dev_kfree_skb_any(skb);
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}
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EXPORT_SYMBOL(ath12k_dp_htt_htc_t2h_msg_handler);
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static int
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ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab,
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int mac_id, u32 ring_id,
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enum hal_ring_type ring_type,
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enum htt_srng_ring_type *htt_ring_type,
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enum htt_srng_ring_id *htt_ring_id)
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{
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int ret = 0;
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switch (ring_type) {
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case HAL_RXDMA_BUF:
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/* for some targets, host fills rx buffer to fw and fw fills to
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* rxbuf ring for each rxdma
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*/
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if (!ab->hw_params->rx_mac_buf_ring) {
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if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 ||
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ring_id == HAL_SRNG_SW2RXDMA_BUF1)) {
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ret = -EINVAL;
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}
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*htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
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*htt_ring_type = HTT_SW_TO_HW_RING;
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} else {
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if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) {
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*htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
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*htt_ring_type = HTT_SW_TO_SW_RING;
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} else {
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*htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
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*htt_ring_type = HTT_SW_TO_HW_RING;
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}
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}
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break;
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case HAL_RXDMA_DST:
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*htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
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*htt_ring_type = HTT_HW_TO_SW_RING;
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break;
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case HAL_RXDMA_MONITOR_BUF:
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*htt_ring_id = HTT_RX_MON_HOST2MON_BUF_RING;
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*htt_ring_type = HTT_SW_TO_HW_RING;
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break;
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case HAL_RXDMA_MONITOR_STATUS:
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*htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
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*htt_ring_type = HTT_SW_TO_HW_RING;
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break;
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case HAL_RXDMA_MONITOR_DST:
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*htt_ring_id = HTT_RX_MON_MON2HOST_DEST_RING;
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*htt_ring_type = HTT_HW_TO_SW_RING;
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break;
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case HAL_RXDMA_MONITOR_DESC:
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*htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
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*htt_ring_type = HTT_SW_TO_HW_RING;
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break;
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default:
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ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
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ret = -EINVAL;
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}
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return ret;
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}
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int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
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int mac_id, enum hal_ring_type ring_type)
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{
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struct htt_srng_setup_cmd *cmd;
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struct hal_srng *srng = &ab->hal.srng_list[ring_id];
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struct hal_srng_params params;
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struct sk_buff *skb;
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u32 ring_entry_sz;
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int len = sizeof(*cmd);
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dma_addr_t hp_addr, tp_addr;
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enum htt_srng_ring_type htt_ring_type;
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enum htt_srng_ring_id htt_ring_id;
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int ret;
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skb = ath12k_htc_alloc_skb(ab, len);
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if (!skb)
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return -ENOMEM;
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memset(¶ms, 0, sizeof(params));
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ath12k_hal_srng_get_params(ab, srng, ¶ms);
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hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng);
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tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng);
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ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
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ring_type, &htt_ring_type,
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&htt_ring_id);
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if (ret)
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goto err_free;
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skb_put(skb, len);
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cmd = (struct htt_srng_setup_cmd *)skb->data;
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cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP,
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HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE);
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if (htt_ring_type == HTT_SW_TO_HW_RING ||
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htt_ring_type == HTT_HW_TO_SW_RING)
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cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id),
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HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
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else
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cmd->info0 |= le32_encode_bits(mac_id,
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HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
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cmd->info0 |= le32_encode_bits(htt_ring_type,
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HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE);
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cmd->info0 |= le32_encode_bits(htt_ring_id,
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HTT_SRNG_SETUP_CMD_INFO0_RING_ID);
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cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr &
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HAL_ADDR_LSB_REG_MASK);
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cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >>
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HAL_ADDR_MSB_REG_SHIFT);
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ret = ath12k_hal_srng_get_entrysize(ab, ring_type);
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if (ret < 0)
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goto err_free;
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ring_entry_sz = ret;
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ring_entry_sz >>= 2;
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cmd->info1 = le32_encode_bits(ring_entry_sz,
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HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE);
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cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz,
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HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE);
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cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
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HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP);
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cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
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HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP);
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cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP),
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HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP);
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if (htt_ring_type == HTT_SW_TO_HW_RING)
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cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS);
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cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr));
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cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr));
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cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr));
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cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr));
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cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr));
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cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr));
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cmd->msi_data = cpu_to_le32(params.msi_data);
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cmd->intr_info =
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le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz,
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HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH);
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cmd->intr_info |=
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le32_encode_bits(params.intr_timer_thres_us >> 3,
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HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH);
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cmd->info2 = 0;
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if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
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cmd->info2 = le32_encode_bits(params.low_threshold,
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HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH);
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}
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ath12k_dbg(ab, ATH12K_DBG_HAL,
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"%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",
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__func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
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cmd->msi_data);
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ath12k_dbg(ab, ATH12K_DBG_HAL,
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"ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",
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ring_id, ring_type, cmd->intr_info, cmd->info2);
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ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
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if (ret)
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goto err_free;
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return 0;
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err_free:
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dev_kfree_skb_any(skb);
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return ret;
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}
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#define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
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int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab)
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{
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struct ath12k_dp *dp = &ab->dp;
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struct sk_buff *skb;
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struct htt_ver_req_cmd *cmd;
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int len = sizeof(*cmd);
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u32 metadata_version;
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int ret;
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init_completion(&dp->htt_tgt_version_received);
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skb = ath12k_htc_alloc_skb(ab, len);
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if (!skb)
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return -ENOMEM;
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skb_put(skb, len);
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cmd = (struct htt_ver_req_cmd *)skb->data;
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cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ,
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HTT_OPTION_TAG);
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metadata_version = ath12k_ftm_mode ? HTT_OPTION_TCL_METADATA_VER_V1 :
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HTT_OPTION_TCL_METADATA_VER_V2;
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cmd->tcl_metadata_version = le32_encode_bits(HTT_TAG_TCL_METADATA_VERSION,
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HTT_OPTION_TAG) |
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le32_encode_bits(HTT_TCL_METADATA_VER_SZ,
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HTT_OPTION_LEN) |
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le32_encode_bits(metadata_version,
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HTT_OPTION_VALUE);
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ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
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if (ret) {
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dev_kfree_skb_any(skb);
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return ret;
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}
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ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
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HTT_TARGET_VERSION_TIMEOUT_HZ);
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if (ret == 0) {
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ath12k_warn(ab, "htt target version request timed out\n");
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return -ETIMEDOUT;
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}
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if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
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ath12k_err(ab, "unsupported htt major version %d supported version is %d\n",
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dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
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return -EOPNOTSUPP;
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}
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return 0;
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}
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int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask)
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{
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struct ath12k_base *ab = ar->ab;
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struct ath12k_dp *dp = &ab->dp;
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struct sk_buff *skb;
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struct htt_ppdu_stats_cfg_cmd *cmd;
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int len = sizeof(*cmd);
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u8 pdev_mask;
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int ret;
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int i;
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for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
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skb = ath12k_htc_alloc_skb(ab, len);
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if (!skb)
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return -ENOMEM;
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skb_put(skb, len);
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cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
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cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG,
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HTT_PPDU_STATS_CFG_MSG_TYPE);
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pdev_mask = 1 << (i + ar->pdev_idx);
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cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID);
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cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK);
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ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
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if (ret) {
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dev_kfree_skb_any(skb);
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return ret;
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}
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}
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return 0;
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}
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int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id,
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int mac_id, enum hal_ring_type ring_type,
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int rx_buf_size,
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struct htt_rx_ring_tlv_filter *tlv_filter)
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{
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struct htt_rx_ring_selection_cfg_cmd *cmd;
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struct hal_srng *srng = &ab->hal.srng_list[ring_id];
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struct hal_srng_params params;
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struct sk_buff *skb;
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int len = sizeof(*cmd);
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enum htt_srng_ring_type htt_ring_type;
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enum htt_srng_ring_id htt_ring_id;
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int ret;
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skb = ath12k_htc_alloc_skb(ab, len);
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if (!skb)
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return -ENOMEM;
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memset(¶ms, 0, sizeof(params));
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ath12k_hal_srng_get_params(ab, srng, ¶ms);
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ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
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ring_type, &htt_ring_type,
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&htt_ring_id);
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if (ret)
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goto err_free;
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skb_put(skb, len);
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cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
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cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
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if (htt_ring_type == HTT_SW_TO_HW_RING ||
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htt_ring_type == HTT_HW_TO_SW_RING)
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cmd->info0 |=
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le32_encode_bits(DP_SW2HW_MACID(mac_id),
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HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
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else
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cmd->info0 |=
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le32_encode_bits(mac_id,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
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cmd->info0 |= le32_encode_bits(htt_ring_id,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
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cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
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HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS);
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cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
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HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS);
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cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID);
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cmd->info0 |=
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le32_encode_bits(tlv_filter->drop_threshold_valid,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL);
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cmd->info0 |= le32_encode_bits(!tlv_filter->rxmon_disable,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON);
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cmd->info1 = le32_encode_bits(rx_buf_size,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE);
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cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_mgmt,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);
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cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_ctrl,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);
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cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_data,
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HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);
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cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0);
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cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1);
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cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2);
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cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3);
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cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter);
|
||||
|
||||
cmd->info2 = le32_encode_bits(tlv_filter->rx_drop_threshold,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(tlv_filter->enable_log_mgmt_type,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(tlv_filter->enable_log_ctrl_type,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(tlv_filter->enable_log_data_type,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE);
|
||||
|
||||
cmd->info3 =
|
||||
le32_encode_bits(tlv_filter->enable_rx_tlv_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET);
|
||||
cmd->info3 |=
|
||||
le32_encode_bits(tlv_filter->rx_tlv_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET);
|
||||
|
||||
if (tlv_filter->offset_valid) {
|
||||
cmd->rx_packet_offset =
|
||||
le32_encode_bits(tlv_filter->rx_packet_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET);
|
||||
|
||||
cmd->rx_packet_offset |=
|
||||
le32_encode_bits(tlv_filter->rx_header_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET);
|
||||
|
||||
cmd->rx_mpdu_offset =
|
||||
le32_encode_bits(tlv_filter->rx_mpdu_end_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET);
|
||||
|
||||
cmd->rx_mpdu_offset |=
|
||||
le32_encode_bits(tlv_filter->rx_mpdu_start_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET);
|
||||
|
||||
cmd->rx_msdu_offset =
|
||||
le32_encode_bits(tlv_filter->rx_msdu_end_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET);
|
||||
|
||||
cmd->rx_msdu_offset |=
|
||||
le32_encode_bits(tlv_filter->rx_msdu_start_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET);
|
||||
|
||||
cmd->rx_attn_offset =
|
||||
le32_encode_bits(tlv_filter->rx_attn_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET);
|
||||
}
|
||||
|
||||
if (tlv_filter->rx_mpdu_start_wmask > 0 &&
|
||||
tlv_filter->rx_msdu_end_wmask > 0) {
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(true,
|
||||
HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET);
|
||||
cmd->rx_mpdu_start_end_mask =
|
||||
le32_encode_bits(tlv_filter->rx_mpdu_start_wmask,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK);
|
||||
/* mpdu_end is not used for any hardwares so far
|
||||
* please assign it in future if any chip is
|
||||
* using through hal ops
|
||||
*/
|
||||
cmd->rx_mpdu_start_end_mask |=
|
||||
le32_encode_bits(tlv_filter->rx_mpdu_end_wmask,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK);
|
||||
cmd->rx_msdu_end_word_mask =
|
||||
le32_encode_bits(tlv_filter->rx_msdu_end_wmask,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK);
|
||||
}
|
||||
|
||||
ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free:
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type,
|
||||
struct htt_ext_stats_cfg_params *cfg_params,
|
||||
u64 cookie)
|
||||
{
|
||||
struct ath12k_base *ab = ar->ab;
|
||||
struct ath12k_dp *dp = &ab->dp;
|
||||
struct sk_buff *skb;
|
||||
struct htt_ext_stats_cfg_cmd *cmd;
|
||||
int len = sizeof(*cmd);
|
||||
int ret;
|
||||
u32 pdev_id;
|
||||
|
||||
skb = ath12k_htc_alloc_skb(ab, len);
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
skb_put(skb, len);
|
||||
|
||||
cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
|
||||
memset(cmd, 0, sizeof(*cmd));
|
||||
cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
|
||||
|
||||
pdev_id = ath12k_mac_get_target_pdev_id(ar);
|
||||
cmd->hdr.pdev_mask = 1 << pdev_id;
|
||||
|
||||
cmd->hdr.stats_type = type;
|
||||
cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0);
|
||||
cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1);
|
||||
cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2);
|
||||
cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3);
|
||||
cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie));
|
||||
cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie));
|
||||
|
||||
ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
|
||||
if (ret) {
|
||||
ath12k_warn(ab, "failed to send htt type stats request: %d",
|
||||
ret);
|
||||
dev_kfree_skb_any(skb);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset)
|
||||
{
|
||||
struct ath12k_base *ab = ar->ab;
|
||||
int ret;
|
||||
|
||||
ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset);
|
||||
if (ret) {
|
||||
ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset)
|
||||
{
|
||||
struct ath12k_base *ab = ar->ab;
|
||||
struct htt_rx_ring_tlv_filter tlv_filter = {};
|
||||
int ret, ring_id, i;
|
||||
|
||||
tlv_filter.offset_valid = false;
|
||||
|
||||
if (!reset) {
|
||||
tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING;
|
||||
|
||||
tlv_filter.drop_threshold_valid = true;
|
||||
tlv_filter.rx_drop_threshold = HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE;
|
||||
|
||||
tlv_filter.enable_log_mgmt_type = true;
|
||||
tlv_filter.enable_log_ctrl_type = true;
|
||||
tlv_filter.enable_log_data_type = true;
|
||||
|
||||
tlv_filter.conf_len_ctrl = HTT_RX_RING_DEFAULT_DMA_LENGTH;
|
||||
tlv_filter.conf_len_mgmt = HTT_RX_RING_DEFAULT_DMA_LENGTH;
|
||||
tlv_filter.conf_len_data = HTT_RX_RING_DEFAULT_DMA_LENGTH;
|
||||
|
||||
tlv_filter.enable_rx_tlv_offset = true;
|
||||
tlv_filter.rx_tlv_offset = HTT_RX_RING_PKT_TLV_OFFSET;
|
||||
|
||||
tlv_filter.pkt_filter_flags0 =
|
||||
HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
|
||||
HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
|
||||
tlv_filter.pkt_filter_flags1 =
|
||||
HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
|
||||
HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
|
||||
tlv_filter.pkt_filter_flags2 =
|
||||
HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
|
||||
HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
|
||||
tlv_filter.pkt_filter_flags3 =
|
||||
HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
|
||||
HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
|
||||
HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
|
||||
HTT_RX_MON_MO_DATA_FILTER_FLASG3;
|
||||
} else {
|
||||
tlv_filter = ath12k_mac_mon_status_filter_default;
|
||||
|
||||
if (ath12k_debugfs_is_extd_rx_stats_enabled(ar))
|
||||
tlv_filter.rx_filter = ath12k_debugfs_rx_filter(ar);
|
||||
}
|
||||
|
||||
if (ab->hw_params->rxdma1_enable) {
|
||||
for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
|
||||
ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id;
|
||||
ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
|
||||
ar->dp.mac_id + i,
|
||||
HAL_RXDMA_MONITOR_DST,
|
||||
DP_RXDMA_REFILL_RING_SIZE,
|
||||
&tlv_filter);
|
||||
if (ret) {
|
||||
ath12k_err(ab,
|
||||
"failed to setup filter for monitor buf %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!reset) {
|
||||
for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
|
||||
ring_id = ab->dp.rx_mac_buf_ring[i].ring_id;
|
||||
ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
|
||||
i,
|
||||
HAL_RXDMA_BUF,
|
||||
DP_RXDMA_REFILL_RING_SIZE,
|
||||
&tlv_filter);
|
||||
if (ret) {
|
||||
ath12k_err(ab,
|
||||
"failed to setup filter for mon rx buf %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
|
||||
ring_id = ab->dp.rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
|
||||
if (!reset) {
|
||||
tlv_filter.rx_filter =
|
||||
HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING;
|
||||
}
|
||||
|
||||
ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id,
|
||||
i,
|
||||
HAL_RXDMA_MONITOR_STATUS,
|
||||
RX_MON_STATUS_BUF_SIZE,
|
||||
&tlv_filter);
|
||||
if (ret) {
|
||||
ath12k_err(ab,
|
||||
"failed to setup filter for mon status buf %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id,
|
||||
int mac_id, enum hal_ring_type ring_type,
|
||||
int tx_buf_size,
|
||||
struct htt_tx_ring_tlv_filter *htt_tlv_filter)
|
||||
{
|
||||
struct htt_tx_ring_selection_cfg_cmd *cmd;
|
||||
struct hal_srng *srng = &ab->hal.srng_list[ring_id];
|
||||
struct hal_srng_params params;
|
||||
struct sk_buff *skb;
|
||||
int len = sizeof(*cmd);
|
||||
enum htt_srng_ring_type htt_ring_type;
|
||||
enum htt_srng_ring_id htt_ring_id;
|
||||
int ret;
|
||||
|
||||
skb = ath12k_htc_alloc_skb(ab, len);
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(¶ms, 0, sizeof(params));
|
||||
ath12k_hal_srng_get_params(ab, srng, ¶ms);
|
||||
|
||||
ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
|
||||
ring_type, &htt_ring_type,
|
||||
&htt_ring_id);
|
||||
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
skb_put(skb, len);
|
||||
cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data;
|
||||
cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
|
||||
if (htt_ring_type == HTT_SW_TO_HW_RING ||
|
||||
htt_ring_type == HTT_HW_TO_SW_RING)
|
||||
cmd->info0 |=
|
||||
le32_encode_bits(DP_SW2HW_MACID(mac_id),
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
|
||||
else
|
||||
cmd->info0 |=
|
||||
le32_encode_bits(mac_id,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
|
||||
cmd->info0 |= le32_encode_bits(htt_ring_id,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
|
||||
cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS);
|
||||
cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS);
|
||||
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(tx_buf_size,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE);
|
||||
|
||||
if (htt_tlv_filter->tx_mon_mgmt_filter) {
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
|
||||
}
|
||||
|
||||
if (htt_tlv_filter->tx_mon_data_filter) {
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
|
||||
}
|
||||
|
||||
if (htt_tlv_filter->tx_mon_ctrl_filter) {
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
|
||||
}
|
||||
|
||||
cmd->tlv_filter_mask_in0 =
|
||||
cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags);
|
||||
cmd->tlv_filter_mask_in1 =
|
||||
cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0);
|
||||
cmd->tlv_filter_mask_in2 =
|
||||
cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1);
|
||||
cmd->tlv_filter_mask_in3 =
|
||||
cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2);
|
||||
|
||||
ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free:
|
||||
dev_kfree_skb_any(skb);
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1514,10 +1514,30 @@ struct htt_mac_addr {
|
|||
__le32 mac_addr_h16;
|
||||
} __packed;
|
||||
|
||||
int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
|
||||
int mac_id, enum hal_ring_type ring_type);
|
||||
|
||||
void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab,
|
||||
struct sk_buff *skb);
|
||||
int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len,
|
||||
int (*iter)(struct ath12k_base *ar, u16 tag, u16 len,
|
||||
const void *ptr, void *data),
|
||||
void *data);
|
||||
void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab,
|
||||
struct sk_buff *skb);
|
||||
int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab);
|
||||
int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask);
|
||||
int
|
||||
ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type,
|
||||
struct htt_ext_stats_cfg_params *cfg_params,
|
||||
u64 cookie);
|
||||
int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset);
|
||||
|
||||
int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id,
|
||||
int mac_id, enum hal_ring_type ring_type,
|
||||
int rx_buf_size,
|
||||
struct htt_rx_ring_tlv_filter *tlv_filter);
|
||||
int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id,
|
||||
int mac_id, enum hal_ring_type ring_type,
|
||||
int tx_buf_size,
|
||||
struct htt_tx_ring_tlv_filter *htt_tlv_filter);
|
||||
int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -200,685 +200,3 @@ void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab,
|
|||
if (atomic_dec_and_test(&ar->dp.num_tx_pending))
|
||||
wake_up(&ar->dp.tx_empty_waitq);
|
||||
}
|
||||
|
||||
static int
|
||||
ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab,
|
||||
int mac_id, u32 ring_id,
|
||||
enum hal_ring_type ring_type,
|
||||
enum htt_srng_ring_type *htt_ring_type,
|
||||
enum htt_srng_ring_id *htt_ring_id)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (ring_type) {
|
||||
case HAL_RXDMA_BUF:
|
||||
/* for some targets, host fills rx buffer to fw and fw fills to
|
||||
* rxbuf ring for each rxdma
|
||||
*/
|
||||
if (!ab->hw_params->rx_mac_buf_ring) {
|
||||
if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 ||
|
||||
ring_id == HAL_SRNG_SW2RXDMA_BUF1)) {
|
||||
ret = -EINVAL;
|
||||
}
|
||||
*htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
|
||||
*htt_ring_type = HTT_SW_TO_HW_RING;
|
||||
} else {
|
||||
if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) {
|
||||
*htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
|
||||
*htt_ring_type = HTT_SW_TO_SW_RING;
|
||||
} else {
|
||||
*htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
|
||||
*htt_ring_type = HTT_SW_TO_HW_RING;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case HAL_RXDMA_DST:
|
||||
*htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
|
||||
*htt_ring_type = HTT_HW_TO_SW_RING;
|
||||
break;
|
||||
case HAL_RXDMA_MONITOR_BUF:
|
||||
*htt_ring_id = HTT_RX_MON_HOST2MON_BUF_RING;
|
||||
*htt_ring_type = HTT_SW_TO_HW_RING;
|
||||
break;
|
||||
case HAL_RXDMA_MONITOR_STATUS:
|
||||
*htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
|
||||
*htt_ring_type = HTT_SW_TO_HW_RING;
|
||||
break;
|
||||
case HAL_RXDMA_MONITOR_DST:
|
||||
*htt_ring_id = HTT_RX_MON_MON2HOST_DEST_RING;
|
||||
*htt_ring_type = HTT_HW_TO_SW_RING;
|
||||
break;
|
||||
case HAL_RXDMA_MONITOR_DESC:
|
||||
*htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
|
||||
*htt_ring_type = HTT_SW_TO_HW_RING;
|
||||
break;
|
||||
default:
|
||||
ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
|
||||
int mac_id, enum hal_ring_type ring_type)
|
||||
{
|
||||
struct htt_srng_setup_cmd *cmd;
|
||||
struct hal_srng *srng = &ab->hal.srng_list[ring_id];
|
||||
struct hal_srng_params params;
|
||||
struct sk_buff *skb;
|
||||
u32 ring_entry_sz;
|
||||
int len = sizeof(*cmd);
|
||||
dma_addr_t hp_addr, tp_addr;
|
||||
enum htt_srng_ring_type htt_ring_type;
|
||||
enum htt_srng_ring_id htt_ring_id;
|
||||
int ret;
|
||||
|
||||
skb = ath12k_htc_alloc_skb(ab, len);
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(¶ms, 0, sizeof(params));
|
||||
ath12k_hal_srng_get_params(ab, srng, ¶ms);
|
||||
|
||||
hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng);
|
||||
tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng);
|
||||
|
||||
ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
|
||||
ring_type, &htt_ring_type,
|
||||
&htt_ring_id);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
skb_put(skb, len);
|
||||
cmd = (struct htt_srng_setup_cmd *)skb->data;
|
||||
cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP,
|
||||
HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE);
|
||||
if (htt_ring_type == HTT_SW_TO_HW_RING ||
|
||||
htt_ring_type == HTT_HW_TO_SW_RING)
|
||||
cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id),
|
||||
HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
|
||||
else
|
||||
cmd->info0 |= le32_encode_bits(mac_id,
|
||||
HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
|
||||
cmd->info0 |= le32_encode_bits(htt_ring_type,
|
||||
HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE);
|
||||
cmd->info0 |= le32_encode_bits(htt_ring_id,
|
||||
HTT_SRNG_SETUP_CMD_INFO0_RING_ID);
|
||||
|
||||
cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr &
|
||||
HAL_ADDR_LSB_REG_MASK);
|
||||
|
||||
cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >>
|
||||
HAL_ADDR_MSB_REG_SHIFT);
|
||||
|
||||
ret = ath12k_hal_srng_get_entrysize(ab, ring_type);
|
||||
if (ret < 0)
|
||||
goto err_free;
|
||||
|
||||
ring_entry_sz = ret;
|
||||
|
||||
ring_entry_sz >>= 2;
|
||||
cmd->info1 = le32_encode_bits(ring_entry_sz,
|
||||
HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE);
|
||||
cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz,
|
||||
HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE);
|
||||
cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
|
||||
HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP);
|
||||
cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
|
||||
HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP);
|
||||
cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP),
|
||||
HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP);
|
||||
if (htt_ring_type == HTT_SW_TO_HW_RING)
|
||||
cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS);
|
||||
|
||||
cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr));
|
||||
cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr));
|
||||
|
||||
cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr));
|
||||
cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr));
|
||||
|
||||
cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr));
|
||||
cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr));
|
||||
cmd->msi_data = cpu_to_le32(params.msi_data);
|
||||
|
||||
cmd->intr_info =
|
||||
le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz,
|
||||
HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH);
|
||||
cmd->intr_info |=
|
||||
le32_encode_bits(params.intr_timer_thres_us >> 3,
|
||||
HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH);
|
||||
|
||||
cmd->info2 = 0;
|
||||
if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
|
||||
cmd->info2 = le32_encode_bits(params.low_threshold,
|
||||
HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH);
|
||||
}
|
||||
|
||||
ath12k_dbg(ab, ATH12K_DBG_HAL,
|
||||
"%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",
|
||||
__func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
|
||||
cmd->msi_data);
|
||||
|
||||
ath12k_dbg(ab, ATH12K_DBG_HAL,
|
||||
"ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",
|
||||
ring_id, ring_type, cmd->intr_info, cmd->info2);
|
||||
|
||||
ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free:
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
|
||||
|
||||
int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab)
|
||||
{
|
||||
struct ath12k_dp *dp = &ab->dp;
|
||||
struct sk_buff *skb;
|
||||
struct htt_ver_req_cmd *cmd;
|
||||
int len = sizeof(*cmd);
|
||||
u32 metadata_version;
|
||||
int ret;
|
||||
|
||||
init_completion(&dp->htt_tgt_version_received);
|
||||
|
||||
skb = ath12k_htc_alloc_skb(ab, len);
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
skb_put(skb, len);
|
||||
cmd = (struct htt_ver_req_cmd *)skb->data;
|
||||
cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ,
|
||||
HTT_OPTION_TAG);
|
||||
metadata_version = ath12k_ftm_mode ? HTT_OPTION_TCL_METADATA_VER_V1 :
|
||||
HTT_OPTION_TCL_METADATA_VER_V2;
|
||||
|
||||
cmd->tcl_metadata_version = le32_encode_bits(HTT_TAG_TCL_METADATA_VERSION,
|
||||
HTT_OPTION_TAG) |
|
||||
le32_encode_bits(HTT_TCL_METADATA_VER_SZ,
|
||||
HTT_OPTION_LEN) |
|
||||
le32_encode_bits(metadata_version,
|
||||
HTT_OPTION_VALUE);
|
||||
|
||||
ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
|
||||
if (ret) {
|
||||
dev_kfree_skb_any(skb);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
|
||||
HTT_TARGET_VERSION_TIMEOUT_HZ);
|
||||
if (ret == 0) {
|
||||
ath12k_warn(ab, "htt target version request timed out\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
|
||||
ath12k_err(ab, "unsupported htt major version %d supported version is %d\n",
|
||||
dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask)
|
||||
{
|
||||
struct ath12k_base *ab = ar->ab;
|
||||
struct ath12k_dp *dp = &ab->dp;
|
||||
struct sk_buff *skb;
|
||||
struct htt_ppdu_stats_cfg_cmd *cmd;
|
||||
int len = sizeof(*cmd);
|
||||
u8 pdev_mask;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
|
||||
skb = ath12k_htc_alloc_skb(ab, len);
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
skb_put(skb, len);
|
||||
cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
|
||||
cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG,
|
||||
HTT_PPDU_STATS_CFG_MSG_TYPE);
|
||||
|
||||
pdev_mask = 1 << (i + ar->pdev_idx);
|
||||
cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID);
|
||||
cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK);
|
||||
|
||||
ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
|
||||
if (ret) {
|
||||
dev_kfree_skb_any(skb);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id,
|
||||
int mac_id, enum hal_ring_type ring_type,
|
||||
int rx_buf_size,
|
||||
struct htt_rx_ring_tlv_filter *tlv_filter)
|
||||
{
|
||||
struct htt_rx_ring_selection_cfg_cmd *cmd;
|
||||
struct hal_srng *srng = &ab->hal.srng_list[ring_id];
|
||||
struct hal_srng_params params;
|
||||
struct sk_buff *skb;
|
||||
int len = sizeof(*cmd);
|
||||
enum htt_srng_ring_type htt_ring_type;
|
||||
enum htt_srng_ring_id htt_ring_id;
|
||||
int ret;
|
||||
|
||||
skb = ath12k_htc_alloc_skb(ab, len);
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(¶ms, 0, sizeof(params));
|
||||
ath12k_hal_srng_get_params(ab, srng, ¶ms);
|
||||
|
||||
ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
|
||||
ring_type, &htt_ring_type,
|
||||
&htt_ring_id);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
skb_put(skb, len);
|
||||
cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
|
||||
cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
|
||||
if (htt_ring_type == HTT_SW_TO_HW_RING ||
|
||||
htt_ring_type == HTT_HW_TO_SW_RING)
|
||||
cmd->info0 |=
|
||||
le32_encode_bits(DP_SW2HW_MACID(mac_id),
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
|
||||
else
|
||||
cmd->info0 |=
|
||||
le32_encode_bits(mac_id,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
|
||||
cmd->info0 |= le32_encode_bits(htt_ring_id,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
|
||||
cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS);
|
||||
cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS);
|
||||
cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID);
|
||||
cmd->info0 |=
|
||||
le32_encode_bits(tlv_filter->drop_threshold_valid,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL);
|
||||
cmd->info0 |= le32_encode_bits(!tlv_filter->rxmon_disable,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON);
|
||||
|
||||
cmd->info1 = le32_encode_bits(rx_buf_size,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE);
|
||||
cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_mgmt,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);
|
||||
cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_ctrl,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);
|
||||
cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_data,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);
|
||||
cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0);
|
||||
cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1);
|
||||
cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2);
|
||||
cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3);
|
||||
cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter);
|
||||
|
||||
cmd->info2 = le32_encode_bits(tlv_filter->rx_drop_threshold,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(tlv_filter->enable_log_mgmt_type,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(tlv_filter->enable_log_ctrl_type,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(tlv_filter->enable_log_data_type,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE);
|
||||
|
||||
cmd->info3 =
|
||||
le32_encode_bits(tlv_filter->enable_rx_tlv_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET);
|
||||
cmd->info3 |=
|
||||
le32_encode_bits(tlv_filter->rx_tlv_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET);
|
||||
|
||||
if (tlv_filter->offset_valid) {
|
||||
cmd->rx_packet_offset =
|
||||
le32_encode_bits(tlv_filter->rx_packet_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET);
|
||||
|
||||
cmd->rx_packet_offset |=
|
||||
le32_encode_bits(tlv_filter->rx_header_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET);
|
||||
|
||||
cmd->rx_mpdu_offset =
|
||||
le32_encode_bits(tlv_filter->rx_mpdu_end_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET);
|
||||
|
||||
cmd->rx_mpdu_offset |=
|
||||
le32_encode_bits(tlv_filter->rx_mpdu_start_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET);
|
||||
|
||||
cmd->rx_msdu_offset =
|
||||
le32_encode_bits(tlv_filter->rx_msdu_end_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET);
|
||||
|
||||
cmd->rx_msdu_offset |=
|
||||
le32_encode_bits(tlv_filter->rx_msdu_start_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET);
|
||||
|
||||
cmd->rx_attn_offset =
|
||||
le32_encode_bits(tlv_filter->rx_attn_offset,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET);
|
||||
}
|
||||
|
||||
if (tlv_filter->rx_mpdu_start_wmask > 0 &&
|
||||
tlv_filter->rx_msdu_end_wmask > 0) {
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(true,
|
||||
HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET);
|
||||
cmd->rx_mpdu_start_end_mask =
|
||||
le32_encode_bits(tlv_filter->rx_mpdu_start_wmask,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK);
|
||||
/* mpdu_end is not used for any hardwares so far
|
||||
* please assign it in future if any chip is
|
||||
* using through hal ops
|
||||
*/
|
||||
cmd->rx_mpdu_start_end_mask |=
|
||||
le32_encode_bits(tlv_filter->rx_mpdu_end_wmask,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK);
|
||||
cmd->rx_msdu_end_word_mask =
|
||||
le32_encode_bits(tlv_filter->rx_msdu_end_wmask,
|
||||
HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK);
|
||||
}
|
||||
|
||||
ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free:
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type,
|
||||
struct htt_ext_stats_cfg_params *cfg_params,
|
||||
u64 cookie)
|
||||
{
|
||||
struct ath12k_base *ab = ar->ab;
|
||||
struct ath12k_dp *dp = &ab->dp;
|
||||
struct sk_buff *skb;
|
||||
struct htt_ext_stats_cfg_cmd *cmd;
|
||||
int len = sizeof(*cmd);
|
||||
int ret;
|
||||
u32 pdev_id;
|
||||
|
||||
skb = ath12k_htc_alloc_skb(ab, len);
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
skb_put(skb, len);
|
||||
|
||||
cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
|
||||
memset(cmd, 0, sizeof(*cmd));
|
||||
cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
|
||||
|
||||
pdev_id = ath12k_mac_get_target_pdev_id(ar);
|
||||
cmd->hdr.pdev_mask = 1 << pdev_id;
|
||||
|
||||
cmd->hdr.stats_type = type;
|
||||
cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0);
|
||||
cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1);
|
||||
cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2);
|
||||
cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3);
|
||||
cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie));
|
||||
cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie));
|
||||
|
||||
ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
|
||||
if (ret) {
|
||||
ath12k_warn(ab, "failed to send htt type stats request: %d",
|
||||
ret);
|
||||
dev_kfree_skb_any(skb);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset)
|
||||
{
|
||||
struct ath12k_base *ab = ar->ab;
|
||||
int ret;
|
||||
|
||||
ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset);
|
||||
if (ret) {
|
||||
ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset)
|
||||
{
|
||||
struct ath12k_base *ab = ar->ab;
|
||||
struct htt_rx_ring_tlv_filter tlv_filter = {};
|
||||
int ret, ring_id, i;
|
||||
|
||||
tlv_filter.offset_valid = false;
|
||||
|
||||
if (!reset) {
|
||||
tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING;
|
||||
|
||||
tlv_filter.drop_threshold_valid = true;
|
||||
tlv_filter.rx_drop_threshold = HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE;
|
||||
|
||||
tlv_filter.enable_log_mgmt_type = true;
|
||||
tlv_filter.enable_log_ctrl_type = true;
|
||||
tlv_filter.enable_log_data_type = true;
|
||||
|
||||
tlv_filter.conf_len_ctrl = HTT_RX_RING_DEFAULT_DMA_LENGTH;
|
||||
tlv_filter.conf_len_mgmt = HTT_RX_RING_DEFAULT_DMA_LENGTH;
|
||||
tlv_filter.conf_len_data = HTT_RX_RING_DEFAULT_DMA_LENGTH;
|
||||
|
||||
tlv_filter.enable_rx_tlv_offset = true;
|
||||
tlv_filter.rx_tlv_offset = HTT_RX_RING_PKT_TLV_OFFSET;
|
||||
|
||||
tlv_filter.pkt_filter_flags0 =
|
||||
HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
|
||||
HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
|
||||
tlv_filter.pkt_filter_flags1 =
|
||||
HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
|
||||
HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
|
||||
tlv_filter.pkt_filter_flags2 =
|
||||
HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
|
||||
HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
|
||||
tlv_filter.pkt_filter_flags3 =
|
||||
HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
|
||||
HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
|
||||
HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
|
||||
HTT_RX_MON_MO_DATA_FILTER_FLASG3;
|
||||
} else {
|
||||
tlv_filter = ath12k_mac_mon_status_filter_default;
|
||||
|
||||
if (ath12k_debugfs_is_extd_rx_stats_enabled(ar))
|
||||
tlv_filter.rx_filter = ath12k_debugfs_rx_filter(ar);
|
||||
}
|
||||
|
||||
if (ab->hw_params->rxdma1_enable) {
|
||||
for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
|
||||
ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id;
|
||||
ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
|
||||
ar->dp.mac_id + i,
|
||||
HAL_RXDMA_MONITOR_DST,
|
||||
DP_RXDMA_REFILL_RING_SIZE,
|
||||
&tlv_filter);
|
||||
if (ret) {
|
||||
ath12k_err(ab,
|
||||
"failed to setup filter for monitor buf %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!reset) {
|
||||
for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
|
||||
ring_id = ab->dp.rx_mac_buf_ring[i].ring_id;
|
||||
ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
|
||||
i,
|
||||
HAL_RXDMA_BUF,
|
||||
DP_RXDMA_REFILL_RING_SIZE,
|
||||
&tlv_filter);
|
||||
if (ret) {
|
||||
ath12k_err(ab,
|
||||
"failed to setup filter for mon rx buf %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
|
||||
ring_id = ab->dp.rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
|
||||
if (!reset) {
|
||||
tlv_filter.rx_filter =
|
||||
HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING;
|
||||
}
|
||||
|
||||
ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id,
|
||||
i,
|
||||
HAL_RXDMA_MONITOR_STATUS,
|
||||
RX_MON_STATUS_BUF_SIZE,
|
||||
&tlv_filter);
|
||||
if (ret) {
|
||||
ath12k_err(ab,
|
||||
"failed to setup filter for mon status buf %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id,
|
||||
int mac_id, enum hal_ring_type ring_type,
|
||||
int tx_buf_size,
|
||||
struct htt_tx_ring_tlv_filter *htt_tlv_filter)
|
||||
{
|
||||
struct htt_tx_ring_selection_cfg_cmd *cmd;
|
||||
struct hal_srng *srng = &ab->hal.srng_list[ring_id];
|
||||
struct hal_srng_params params;
|
||||
struct sk_buff *skb;
|
||||
int len = sizeof(*cmd);
|
||||
enum htt_srng_ring_type htt_ring_type;
|
||||
enum htt_srng_ring_id htt_ring_id;
|
||||
int ret;
|
||||
|
||||
skb = ath12k_htc_alloc_skb(ab, len);
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(¶ms, 0, sizeof(params));
|
||||
ath12k_hal_srng_get_params(ab, srng, ¶ms);
|
||||
|
||||
ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
|
||||
ring_type, &htt_ring_type,
|
||||
&htt_ring_id);
|
||||
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
skb_put(skb, len);
|
||||
cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data;
|
||||
cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
|
||||
if (htt_ring_type == HTT_SW_TO_HW_RING ||
|
||||
htt_ring_type == HTT_HW_TO_SW_RING)
|
||||
cmd->info0 |=
|
||||
le32_encode_bits(DP_SW2HW_MACID(mac_id),
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
|
||||
else
|
||||
cmd->info0 |=
|
||||
le32_encode_bits(mac_id,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
|
||||
cmd->info0 |= le32_encode_bits(htt_ring_id,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
|
||||
cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS);
|
||||
cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS);
|
||||
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(tx_buf_size,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE);
|
||||
|
||||
if (htt_tlv_filter->tx_mon_mgmt_filter) {
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
|
||||
}
|
||||
|
||||
if (htt_tlv_filter->tx_mon_data_filter) {
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
|
||||
}
|
||||
|
||||
if (htt_tlv_filter->tx_mon_ctrl_filter) {
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
|
||||
cmd->info1 |=
|
||||
le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);
|
||||
cmd->info2 |=
|
||||
le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
|
||||
HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
|
||||
}
|
||||
|
||||
cmd->tlv_filter_mask_in0 =
|
||||
cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags);
|
||||
cmd->tlv_filter_mask_in1 =
|
||||
cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0);
|
||||
cmd->tlv_filter_mask_in2 =
|
||||
cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1);
|
||||
cmd->tlv_filter_mask_in3 =
|
||||
cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2);
|
||||
|
||||
ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free:
|
||||
dev_kfree_skb_any(skb);
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,25 +15,7 @@ struct ath12k_dp_htt_wbm_tx_status {
|
|||
s8 ack_rssi;
|
||||
};
|
||||
|
||||
int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab);
|
||||
int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask);
|
||||
int
|
||||
ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type,
|
||||
struct htt_ext_stats_cfg_params *cfg_params,
|
||||
u64 cookie);
|
||||
int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset);
|
||||
|
||||
int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id,
|
||||
int mac_id, enum hal_ring_type ring_type,
|
||||
int rx_buf_size,
|
||||
struct htt_rx_ring_tlv_filter *tlv_filter);
|
||||
void ath12k_dp_tx_put_bank_profile(struct ath12k_dp *dp, u8 bank_id);
|
||||
int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id,
|
||||
int mac_id, enum hal_ring_type ring_type,
|
||||
int tx_buf_size,
|
||||
struct htt_tx_ring_tlv_filter *htt_tlv_filter);
|
||||
int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset);
|
||||
|
||||
enum hal_tcl_encap_type
|
||||
ath12k_dp_tx_get_encap_type(struct ath12k_base *ab, struct sk_buff *skb);
|
||||
void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user