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Merge patch series "ufs: host: mediatek: Provide features and fixes in MediaTek platforms"
peter.wang@mediatek.com says: This series fixes some defects and provide features in MediaTek UFS drivers. Link: https://lore.kernel.org/r/20250722030841.1998783-1-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Martin K. Petersen
commit
60feab054b
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@ -96,49 +96,59 @@ static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return !!(host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE);
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return host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
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}
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static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return !!(host->caps & UFS_MTK_CAP_VA09_PWR_CTRL);
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return host->caps & UFS_MTK_CAP_VA09_PWR_CTRL;
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}
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static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return !!(host->caps & UFS_MTK_CAP_BROKEN_VCC);
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return host->caps & UFS_MTK_CAP_BROKEN_VCC;
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}
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static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);
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return host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO;
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}
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static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return (host->caps & UFS_MTK_CAP_TX_SKEW_FIX);
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return host->caps & UFS_MTK_CAP_TX_SKEW_FIX;
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}
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static bool ufs_mtk_is_rtff_mtcmos(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return (host->caps & UFS_MTK_CAP_RTFF_MTCMOS);
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return host->caps & UFS_MTK_CAP_RTFF_MTCMOS;
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}
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static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return (host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);
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return host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM;
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}
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static bool ufs_mtk_is_clk_scale_ready(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct ufs_mtk_clk *mclk = &host->mclk;
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return mclk->ufs_sel_clki &&
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mclk->ufs_sel_max_clki &&
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mclk->ufs_sel_min_clki;
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}
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static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
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@ -267,6 +277,13 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
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ufshcd_writel(hba,
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ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80,
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REG_UFS_XOUFS_CTRL);
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/* DDR_EN setting */
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if (host->ip_ver >= IP_VER_MT6989) {
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ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8),
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0x453000, REG_UFS_MMIO_OPT_CTRL_0);
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}
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}
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return 0;
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@ -344,7 +361,16 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
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dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
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ufs_mtk_ref_clk_notify(host->ref_clk_enabled, POST_CHANGE, res);
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/*
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* If clock on timeout, assume clock is off, notify tfa do clock
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* off setting.(keep DIFN disable, release resource)
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* If clock off timeout, assume clock will off finally,
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* set ref_clk_enabled directly.(keep DIFN disable, keep resource)
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*/
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if (on)
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ufs_mtk_ref_clk_notify(false, POST_CHANGE, res);
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else
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host->ref_clk_enabled = false;
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return -ETIMEDOUT;
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@ -663,6 +689,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
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if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos"))
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host->caps |= UFS_MTK_CAP_RTFF_MTCMOS;
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if (of_property_read_bool(np, "mediatek,ufs-broken-rtc"))
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host->caps |= UFS_MTK_CAP_MCQ_BROKEN_RTC;
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dev_info(hba->dev, "caps: 0x%x", host->caps);
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}
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@ -779,6 +808,91 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
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return ret;
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}
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static u32 ufs_mtk_mcq_get_irq(struct ufs_hba *hba, unsigned int cpu)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct blk_mq_tag_set *tag_set = &hba->host->tag_set;
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struct blk_mq_queue_map *map = &tag_set->map[HCTX_TYPE_DEFAULT];
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unsigned int nr = map->nr_queues;
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unsigned int q_index;
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q_index = map->mq_map[cpu];
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if (q_index > nr) {
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dev_err(hba->dev, "hwq index %d exceed %d\n",
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q_index, nr);
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return MTK_MCQ_INVALID_IRQ;
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}
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return host->mcq_intr_info[q_index].irq;
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}
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static void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba, unsigned int cpu)
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{
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unsigned int irq, _cpu;
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int ret;
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irq = ufs_mtk_mcq_get_irq(hba, cpu);
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if (irq == MTK_MCQ_INVALID_IRQ) {
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dev_err(hba->dev, "invalid irq. unable to bind irq to cpu%d", cpu);
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return;
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}
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/* force migrate irq of cpu0 to cpu3 */
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_cpu = (cpu == 0) ? 3 : cpu;
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ret = irq_set_affinity(irq, cpumask_of(_cpu));
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if (ret) {
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dev_err(hba->dev, "set irq %d affinity to CPU %d failed\n",
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irq, _cpu);
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return;
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}
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dev_info(hba->dev, "set irq %d affinity to CPU: %d\n", irq, _cpu);
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}
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static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver)
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{
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bool is_legacy = false;
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switch (hw_ip_ver) {
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case IP_LEGACY_VER_MT6893:
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case IP_LEGACY_VER_MT6781:
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/* can add other legacy chipset ID here accordingly */
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is_legacy = true;
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break;
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default:
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break;
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}
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dev_info(hba->dev, "legacy IP version - 0x%x, is legacy : %d", hw_ip_ver, is_legacy);
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return is_legacy;
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}
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/*
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* HW version format has been changed from 01MMmmmm to 1MMMmmmm, since
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* project MT6878. In order to perform correct version comparison,
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* version number is changed by SW for the following projects.
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* IP_VER_MT6983 0x00360000 to 0x10360000
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* IP_VER_MT6897 0x01440000 to 0x10440000
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* IP_VER_MT6989 0x01450000 to 0x10450000
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* IP_VER_MT6991 0x01460000 to 0x10460000
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*/
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static void ufs_mtk_get_hw_ip_version(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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u32 hw_ip_ver;
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hw_ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
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if (((hw_ip_ver & (0xFF << 24)) == (0x1 << 24)) ||
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((hw_ip_ver & (0xFF << 24)) == 0)) {
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hw_ip_ver &= ~(0xFF << 24);
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hw_ip_ver |= (0x1 << 28);
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}
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host->ip_ver = hw_ip_ver;
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host->legacy_ip_ver = ufs_mtk_is_legacy_chipset(hba, hw_ip_ver);
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}
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static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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@ -818,8 +932,10 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct list_head *head = &hba->clk_list_head;
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struct ufs_mtk_clk *mclk = &host->mclk;
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struct ufs_clk_info *clki, *clki_tmp;
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struct device *dev = hba->dev;
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struct regulator *reg;
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u32 volt;
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/*
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* Find private clocks and store them in struct ufs_mtk_clk.
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@ -837,15 +953,57 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
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host->mclk.ufs_sel_min_clki = clki;
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clk_disable_unprepare(clki->clk);
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list_del(&clki->list);
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} else if (!strcmp(clki->name, "ufs_fde")) {
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host->mclk.ufs_fde_clki = clki;
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} else if (!strcmp(clki->name, "ufs_fde_max_src")) {
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host->mclk.ufs_fde_max_clki = clki;
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clk_disable_unprepare(clki->clk);
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list_del(&clki->list);
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} else if (!strcmp(clki->name, "ufs_fde_min_src")) {
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host->mclk.ufs_fde_min_clki = clki;
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clk_disable_unprepare(clki->clk);
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list_del(&clki->list);
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}
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}
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if (!mclk->ufs_sel_clki || !mclk->ufs_sel_max_clki ||
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!mclk->ufs_sel_min_clki) {
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list_for_each_entry(clki, head, list) {
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dev_info(hba->dev, "clk \"%s\" present", clki->name);
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}
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if (!ufs_mtk_is_clk_scale_ready(hba)) {
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hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
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dev_info(hba->dev,
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"%s: Clk-scaling not ready. Feature disabled.",
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__func__);
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return;
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}
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/*
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* Default get vcore if dts have these settings.
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* No matter clock scaling support or not. (may disable by customer)
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*/
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reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
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if (IS_ERR(reg)) {
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dev_info(dev, "failed to get dvfsrc-vcore: %ld",
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PTR_ERR(reg));
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return;
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}
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if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min",
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&volt)) {
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dev_info(dev, "failed to get clk-scale-up-vcore-min");
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return;
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}
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host->mclk.reg_vcore = reg;
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host->mclk.vcore_volt = volt;
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/* If default boot is max gear, request vcore */
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if (reg && volt && host->clk_scale_up) {
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if (regulator_set_voltage(reg, volt, INT_MAX)) {
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dev_info(hba->dev,
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"Failed to set vcore to %d\n", volt);
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}
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}
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}
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@ -1014,13 +1172,17 @@ static int ufs_mtk_init(struct ufs_hba *hba)
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/* Enable clk scaling*/
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hba->caps |= UFSHCD_CAP_CLK_SCALING;
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host->clk_scale_up = true; /* default is max freq */
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/* Set runtime pm delay to replace default */
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shost->rpm_autosuspend_delay = MTK_RPM_AUTOSUSPEND_DELAY_MS;
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hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
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hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_INTR;
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hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_RTC;
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if (host->caps & UFS_MTK_CAP_MCQ_BROKEN_RTC)
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hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_RTC;
|
||||
|
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hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
|
||||
|
||||
if (host->caps & UFS_MTK_CAP_DISABLE_AH8)
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||||
|
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@ -1050,7 +1212,7 @@ static int ufs_mtk_init(struct ufs_hba *hba)
|
|||
|
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ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
|
||||
|
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host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
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ufs_mtk_get_hw_ip_version(hba);
|
||||
|
||||
goto out;
|
||||
|
||||
|
|
@ -1505,6 +1667,13 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
|
|||
{
|
||||
struct ufs_dev_info *dev_info = &hba->dev_info;
|
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u16 mid = dev_info->wmanufacturerid;
|
||||
unsigned int cpu;
|
||||
|
||||
if (hba->mcq_enabled) {
|
||||
/* Iterate all cpus to set affinity for mcq irqs */
|
||||
for (cpu = 0; cpu < nr_cpu_ids; cpu++)
|
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ufs_mtk_mcq_set_irq_affinity(hba, cpu);
|
||||
}
|
||||
|
||||
if (mid == UFS_VENDOR_SAMSUNG) {
|
||||
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
|
||||
|
|
@ -1598,6 +1767,107 @@ static void ufs_mtk_config_scaling_param(struct ufs_hba *hba,
|
|||
hba->vps->ondemand_data.downdifferential = 20;
|
||||
}
|
||||
|
||||
static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
|
||||
{
|
||||
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
|
||||
struct ufs_mtk_clk *mclk = &host->mclk;
|
||||
struct ufs_clk_info *clki = mclk->ufs_sel_clki;
|
||||
struct ufs_clk_info *fde_clki = mclk->ufs_fde_clki;
|
||||
struct regulator *reg;
|
||||
int volt, ret = 0;
|
||||
bool clk_bind_vcore = false;
|
||||
bool clk_fde_scale = false;
|
||||
|
||||
if (!hba->clk_scaling.is_initialized)
|
||||
return;
|
||||
|
||||
if (!clki || !fde_clki)
|
||||
return;
|
||||
|
||||
reg = host->mclk.reg_vcore;
|
||||
volt = host->mclk.vcore_volt;
|
||||
if (reg && volt != 0)
|
||||
clk_bind_vcore = true;
|
||||
|
||||
if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki)
|
||||
clk_fde_scale = true;
|
||||
|
||||
ret = clk_prepare_enable(clki->clk);
|
||||
if (ret) {
|
||||
dev_info(hba->dev,
|
||||
"clk_prepare_enable() fail, ret: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
if (clk_fde_scale) {
|
||||
ret = clk_prepare_enable(fde_clki->clk);
|
||||
if (ret) {
|
||||
dev_info(hba->dev,
|
||||
"fde clk_prepare_enable() fail, ret: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (scale_up) {
|
||||
if (clk_bind_vcore) {
|
||||
ret = regulator_set_voltage(reg, volt, INT_MAX);
|
||||
if (ret) {
|
||||
dev_info(hba->dev,
|
||||
"Failed to set vcore to %d\n", volt);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk);
|
||||
if (ret) {
|
||||
dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
|
||||
ret);
|
||||
}
|
||||
|
||||
if (clk_fde_scale) {
|
||||
ret = clk_set_parent(fde_clki->clk,
|
||||
mclk->ufs_fde_max_clki->clk);
|
||||
if (ret) {
|
||||
dev_info(hba->dev,
|
||||
"Failed to set fde clk mux, ret = %d\n",
|
||||
ret);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (clk_fde_scale) {
|
||||
ret = clk_set_parent(fde_clki->clk,
|
||||
mclk->ufs_fde_min_clki->clk);
|
||||
if (ret) {
|
||||
dev_info(hba->dev,
|
||||
"Failed to set fde clk mux, ret = %d\n",
|
||||
ret);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk);
|
||||
if (ret) {
|
||||
dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
|
||||
ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (clk_bind_vcore) {
|
||||
ret = regulator_set_voltage(reg, 0, INT_MAX);
|
||||
if (ret) {
|
||||
dev_info(hba->dev,
|
||||
"failed to set vcore to MIN\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
clk_disable_unprepare(clki->clk);
|
||||
|
||||
if (clk_fde_scale)
|
||||
clk_disable_unprepare(fde_clki->clk);
|
||||
}
|
||||
|
||||
/**
|
||||
* ufs_mtk_clk_scale - Internal clk scaling operation
|
||||
*
|
||||
|
|
@ -1615,30 +1885,23 @@ static void ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
|
|||
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
|
||||
struct ufs_mtk_clk *mclk = &host->mclk;
|
||||
struct ufs_clk_info *clki = mclk->ufs_sel_clki;
|
||||
int ret = 0;
|
||||
|
||||
ret = clk_prepare_enable(clki->clk);
|
||||
if (ret) {
|
||||
dev_info(hba->dev,
|
||||
"clk_prepare_enable() fail, ret: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
if (host->clk_scale_up == scale_up)
|
||||
goto out;
|
||||
|
||||
if (scale_up) {
|
||||
ret = clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk);
|
||||
if (scale_up)
|
||||
_ufs_mtk_clk_scale(hba, true);
|
||||
else
|
||||
_ufs_mtk_clk_scale(hba, false);
|
||||
|
||||
host->clk_scale_up = scale_up;
|
||||
|
||||
/* Must always set before clk_set_rate() */
|
||||
if (scale_up)
|
||||
clki->curr_freq = clki->max_freq;
|
||||
} else {
|
||||
ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk);
|
||||
else
|
||||
clki->curr_freq = clki->min_freq;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
dev_info(hba->dev,
|
||||
"Failed to set ufs_sel_clki, ret: %d\n", ret);
|
||||
}
|
||||
|
||||
clk_disable_unprepare(clki->clk);
|
||||
|
||||
out:
|
||||
trace_ufs_mtk_clk_scale(clki->name, scale_up, clk_get_rate(clki->clk));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -133,6 +133,8 @@ enum ufs_mtk_host_caps {
|
|||
UFS_MTK_CAP_DISABLE_MCQ = 1 << 8,
|
||||
/* Control MTCMOS with RTFF */
|
||||
UFS_MTK_CAP_RTFF_MTCMOS = 1 << 9,
|
||||
|
||||
UFS_MTK_CAP_MCQ_BROKEN_RTC = 1 << 10,
|
||||
};
|
||||
|
||||
struct ufs_mtk_crypt_cfg {
|
||||
|
|
@ -147,6 +149,11 @@ struct ufs_mtk_clk {
|
|||
struct ufs_clk_info *ufs_sel_clki; /* Mux */
|
||||
struct ufs_clk_info *ufs_sel_max_clki; /* Max src */
|
||||
struct ufs_clk_info *ufs_sel_min_clki; /* Min src */
|
||||
struct ufs_clk_info *ufs_fde_clki; /* Mux */
|
||||
struct ufs_clk_info *ufs_fde_max_clki; /* Max src */
|
||||
struct ufs_clk_info *ufs_fde_min_clki; /* Min src */
|
||||
struct regulator *reg_vcore;
|
||||
int vcore_volt;
|
||||
};
|
||||
|
||||
struct ufs_mtk_hw_ver {
|
||||
|
|
@ -176,9 +183,11 @@ struct ufs_mtk_host {
|
|||
bool mphy_powered_on;
|
||||
bool unipro_lpm;
|
||||
bool ref_clk_enabled;
|
||||
bool clk_scale_up;
|
||||
u16 ref_clk_ungating_wait_us;
|
||||
u16 ref_clk_gating_wait_us;
|
||||
u32 ip_ver;
|
||||
bool legacy_ip_ver;
|
||||
|
||||
bool mcq_set_intr;
|
||||
bool is_mcq_intr_enabled;
|
||||
|
|
@ -192,4 +201,27 @@ struct ufs_mtk_host {
|
|||
/* MTK RTT support number */
|
||||
#define MTK_MAX_NUM_RTT 2
|
||||
|
||||
/* UFSHCI MTK ip version value */
|
||||
enum {
|
||||
/* UFSHCI 3.1 */
|
||||
IP_VER_MT6983 = 0x10360000,
|
||||
IP_VER_MT6878 = 0x10420200,
|
||||
|
||||
/* UFSHCI 4.0 */
|
||||
IP_VER_MT6897 = 0x10440000,
|
||||
IP_VER_MT6989 = 0x10450000,
|
||||
IP_VER_MT6899 = 0x10450100,
|
||||
IP_VER_MT6991_A0 = 0x10460000,
|
||||
IP_VER_MT6991_B0 = 0x10470000,
|
||||
IP_VER_MT6993 = 0x10480000,
|
||||
|
||||
IP_VER_NONE = 0xFFFFFFFF
|
||||
};
|
||||
|
||||
enum ip_ver_legacy {
|
||||
IP_LEGACY_VER_MT6781 = 0x10380000,
|
||||
IP_LEGACY_VER_MT6879 = 0x10360000,
|
||||
IP_LEGACY_VER_MT6893 = 0x20160706
|
||||
};
|
||||
|
||||
#endif /* !_UFS_MEDIATEK_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user