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arm64: Avoid #define'ing PTE_MAYBE_NG to 0x0 for asm use
The PROT_* macros resolve to expressions that are only valid in C and not in assembler, and so they are only usable from C code. Currently, we make an exception for the permission indirection init code in proc.S, which doesn't care about the bits that are conditionally set, and so we just #define PTE_MAYBE_NG to 0x0 for any assembler file that includes these definitions. This is dodgy because this means that PROT_NORMAL and friends is generally available in asm code, but defined in a way that deviates from the definition that C code will observe, which might lead to hard to diagnose issues down the road. So instead, #define PTE_MAYBE_NG only in the place where the PIE constants are evaluated, and #undef it again right after. This allows us to drop the #define from pgtable-prot.h, and avoid the risk of deviating definitions between asm and C. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20240214122845.2033971-72-ardb+git@google.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -57,10 +57,6 @@
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#define _PAGE_READONLY_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
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#define _PAGE_EXECONLY (_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
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#ifdef __ASSEMBLY__
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#define PTE_MAYBE_NG 0
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#endif
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#ifndef __ASSEMBLY__
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#include <asm/cpufeature.h>
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@ -456,11 +456,24 @@ alternative_else_nop_endif
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ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
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cbz x1, .Lskip_indirection
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/*
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* The PROT_* macros describing the various memory types may resolve to
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* C expressions if they include the PTE_MAYBE_* macros, and so they
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* can only be used from C code. The PIE_E* constants below are also
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* defined in terms of those macros, but will mask out those
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* PTE_MAYBE_* constants, whether they are set or not. So #define them
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* as 0x0 here so we can evaluate the PIE_E* constants in asm context.
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*/
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#define PTE_MAYBE_NG 0
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mov_q x0, PIE_E0
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msr REG_PIRE0_EL1, x0
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mov_q x0, PIE_E1
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msr REG_PIR_EL1, x0
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#undef PTE_MAYBE_NG
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mov x0, TCR2_EL1x_PIE
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msr REG_TCR2_EL1, x0
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