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irqchip/qcom-pdc: Move all static variables to struct pdc_desc

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There are multiple static variables used in the driver. Move all to struct
pdc_desc to better align with versioning support. Document them.

Add a new pdc->enable_intr() callback to point to the respective versions
specific enable function. Remove pdc_enable_intr() and __pdc_enable_intr()
and invoke pdc->enable_intr() from the call sites.

Locking in pdc_enable_intr() applies lock to all version specific
pdc->enable_intr() however lock is needed only for pdc_enable_intr_bank()
which uses a shared bank across on PDC v2.7 and PDC v3.0.

pdc_enable_intr_cfg() do not require locking as IRQ_CFG registers are one
per interrupt. Move the locking to pdc_enable_intr_bank().

No functional impact intended

[ tglx: Massage change log. ]

Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-2-dfd1f4a3ae89@oss.qualcomm.com
This commit is contained in:
Maulik Shah 2026-07-07 14:51:34 +05:30 committed by Thomas Gleixner
parent 83e089ef0d
commit 60caa95aa1
1 changed files with 41 additions and 43 deletions
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84
drivers/irqchip/qcom-pdc.c
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@ -92,15 +92,30 @@ struct pdc_irq_cfg {
* @base: PDC base register for DRV2 / HLOS
* @prev_base: PDC DRV1 base, applicable only for x1e RTL bug.
* @version: PDC version
* @region: PDC interrupt continuous range
* @region_cnt: Total PDC ranges
* @x1e_quirk: x1e H/W Bug handling
* @lock: lock for IRQ_ENABLE_BANK protection
* @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG)
* @cfg_fields: Fields of IRQ_CFG reg
* @enable_intr: pointer to enable function based on PDC version
*/
struct pdc_desc {
void __iomem *base;
void __iomem *prev_base;
u32 version;
struct pdc_pin_region *region;
int region_cnt;
bool x1e_quirk;
raw_spinlock_t lock;
const struct pdc_regs *regs;
const struct pdc_irq_cfg *cfg_fields;
void (*enable_intr)(int pin_out, bool on);
};
static const struct pdc_regs pdc_v3_2 = {
@ -138,11 +153,6 @@ struct pdc_pin_region {
#define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
static DEFINE_RAW_SPINLOCK(pdc_lock);
static struct pdc_pin_region *pdc_region;
static int pdc_region_cnt;
static unsigned int pdc_version;
static bool pdc_x1e_quirk;
static struct pdc_desc *pdc;
static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val)
@ -196,10 +206,12 @@ static void pdc_enable_intr_bank(int pin_out, bool on)
index = FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out);
mask = FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out);
guard(raw_spinlock_irqsave)(&pdc->lock);
enable = pdc_reg_read(pdc->regs->irq_en_reg, index);
__assign_bit(mask, &enable, on);
if (pdc_x1e_quirk)
if (pdc->x1e_quirk)
pdc_x1e_irq_enable_write(index, enable);
else
pdc_reg_write(pdc->regs->irq_en_reg, index, enable);
@ -213,32 +225,15 @@ static void pdc_enable_intr_cfg(int pin_out, bool on)
pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable);
}
static void __pdc_enable_intr(int pin_out, bool on)
{
if (pdc_version < PDC_VERSION_3_2)
pdc_enable_intr_bank(pin_out, on);
else
pdc_enable_intr_cfg(pin_out, on);
}
static void pdc_enable_intr(struct irq_data *d, bool on)
{
unsigned long flags;
raw_spin_lock_irqsave(&pdc_lock, flags);
__pdc_enable_intr(d->hwirq, on);
raw_spin_unlock_irqrestore(&pdc_lock, flags);
}
static void qcom_pdc_gic_disable(struct irq_data *d)
{
pdc_enable_intr(d, false);
pdc->enable_intr(d->hwirq, false);
irq_chip_disable_parent(d);
}
static void qcom_pdc_gic_enable(struct irq_data *d)
{
pdc_enable_intr(d, true);
pdc->enable_intr(d->hwirq, true);
irq_chip_enable_parent(d);
}
@ -350,12 +345,10 @@ static struct irq_chip qcom_pdc_gic_chip = {
static struct pdc_pin_region *get_pin_region(int pin)
{
int i;
for (i = 0; i < pdc_region_cnt; i++) {
if (pin >= pdc_region[i].pin_base &&
pin < pdc_region[i].pin_base + pdc_region[i].cnt)
return &pdc_region[i];
for (int i = 0; i < pdc->region_cnt; i++) {
if (pin >= pdc->region[i].pin_base &&
pin < pdc->region[i].pin_base + pdc->region[i].cnt)
return &pdc->region[i];
}
return NULL;
@ -411,35 +404,35 @@ static const struct irq_domain_ops qcom_pdc_ops = {
static int pdc_setup_pin_mapping(struct device *dev)
{
struct device_node *np = dev->of_node;
int ret, n, i;
int ret, n;
n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
if (n <= 0 || n % 3)
return -EINVAL;
pdc_region_cnt = n / 3;
pdc_region = devm_kcalloc(dev, pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
if (!pdc_region) {
pdc_region_cnt = 0;
pdc->region_cnt = n / 3;
pdc->region = devm_kcalloc(dev, pdc->region_cnt, sizeof(*pdc->region), GFP_KERNEL);
if (!pdc->region) {
pdc->region_cnt = 0;
return -ENOMEM;
}
for (n = 0; n < pdc_region_cnt; n++) {
for (n = 0; n < pdc->region_cnt; n++) {
ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 0,
&pdc_region[n].pin_base);
&pdc->region[n].pin_base);
if (ret)
return ret;
ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 1,
&pdc_region[n].parent_base);
&pdc->region[n].parent_base);
if (ret)
return ret;
ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 2,
&pdc_region[n].cnt);
&pdc->region[n].cnt);
if (ret)
return ret;
for (i = 0; i < pdc_region[n].cnt; i++)
__pdc_enable_intr(i + pdc_region[n].pin_base, 0);
for (int i = 0; i < pdc->region[n].cnt; i++)
pdc->enable_intr(i + pdc->region[n].pin_base, 0);
}
return 0;
@ -477,12 +470,15 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare
if (pdc->version >= PDC_VERSION_3_2) {
pdc->cfg_fields = &pdc_cfg_v3_2;
pdc->regs = &pdc_v3_2;
pdc->enable_intr = pdc_enable_intr_cfg;
} else if (pdc->version >= PDC_VERSION_3_0) {
pdc->cfg_fields = &pdc_cfg_v3_0;
pdc->regs = &pdc_v3_0;
pdc->enable_intr = pdc_enable_intr_bank;
} else {
pdc->cfg_fields = &pdc_cfg_v2_7;
pdc->regs = &pdc_v2_7;
pdc->enable_intr = pdc_enable_intr_bank;
}
/*
@ -501,7 +497,7 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare
return -ENXIO;
}
pdc_x1e_quirk = true;
pdc->x1e_quirk = true;
}
parent_domain = irq_find_host(parent);
@ -510,6 +506,8 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare
return -ENXIO;
}
raw_spin_lock_init(&pdc->lock);
ret = pdc_setup_pin_mapping(dev);
if (ret) {
pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);