From 36ca3c8ccb537ac6311b977e71040b493f168a63 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 7 Nov 2020 08:48:09 -0600 Subject: [PATCH 01/71] arm64: dts: imx: Add Beacon i.MX8M Nano development kit Beacon Embeddedworks is launching a development kit based on the i.MX8M Nano SoC. The kit consists of a System on Module (SOM) + baseboard. The SOM has the SoC, eMMC, and Ethernet. The baseboard has an wm8962 audio CODEC, a PDM microphone, and a single USB OTG. The baseboard is capable of two different, mutually exclusive video outputs, so the common items are in the baseboard file. When the video becomes available, LVDS output will be added to this kit file, and a second kit file will be added to support HDMI. Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mn-beacon-baseboard.dtsi | 307 +++++++++++++ .../boot/dts/freescale/imx8mn-beacon-kit.dts | 19 + .../boot/dts/freescale/imx8mn-beacon-som.dtsi | 433 ++++++++++++++++++ 4 files changed, 760 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 6f0777ee6cd6..901d80086b47 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi new file mode 100644 index 000000000000..376ca8ff7213 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + leds { + compatible = "gpio-leds"; + + led-0 { + label = "gen_led0"; + gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "gen_led1"; + gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "gen_led2"; + gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led3>; + label = "heartbeat"; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "vsd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_espi2>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeprom@0 { + compatible = "microchip,at25160bn", "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + pagesize = <32>; + size = <2048>; + address-width = <16>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pca6416_0: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6414>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6416_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + clock-names = "xclk"; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg_vbus>; + disable-over-current; + dr_mode="otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_led3: led3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 + >; + }; + + pinctrl_pcal6414: pcal6414-gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 + >; + }; + + pinctrl_reg_usb_otg: reg-otggrp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts new file mode 100644 index 000000000000..1392ce02587b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-beacon-som.dtsi" +#include "imx8mn-beacon-baseboard.dtsi" + +/ { + model = "Beacon EmbeddedWorks i.MX8M Nano Development Kit"; + compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi new file mode 100644 index 000000000000..67e5e5b9ddea --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + clocks = <&osc_32k>; + clock-names = "ext_clock"; + post-power-on-delay-ms = <80>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +/* DDR controller is running LPDDR at 800MHz which requires 0.95V */ +&a53_opp_table { + opp-1200000000 { + opp-microvolt = <950000>; + }; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-supply = <&buck6_reg>; + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + eeprom@50 { + compatible = "microchip,24c64", "atmel,24c64"; + pagesize = <32>; + read-only; /* Manufacturing EEPROM programmed at factory */ + reg = <0x50>; + }; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + clocks = <&osc_32k>; + max-speed = <4000000>; + clock-names = "extclk"; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + cap-power-off-card; + pm-ignore-notify; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; +}; From 3f8c61a567ebc4c03caba2730352833edc16b132 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 30 Nov 2020 18:15:06 +0800 Subject: [PATCH 02/71] arm64: dts: ls1043a: add DT node for external interrupt lines Add device-tree node for external interrupt lines IRQ0-IRQ11. Signed-off-by: Biwen Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index bbae4b353d3f..12bd1263158f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -311,6 +311,31 @@ scfg: scfg@1570000 { compatible = "fsl,ls1043a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; big-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1570000 0x10000>; + + extirq: interrupt-controller@1ac { + compatible = "fsl,ls1043a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1ac 4>; + interrupt-map = + <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xffffffff 0x0>; + }; }; crypto: crypto@1700000 { From 7968344126e562be585d944be52bfc42e0760a7d Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 30 Nov 2020 18:15:07 +0800 Subject: [PATCH 03/71] arm64: dts: ls1046a: add DT node for external interrupt lines Add device-tree node for external interrupt lines IRQ0-IRQ11. Signed-off-by: Biwen Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 025e1f587662..d3f5e48c58dd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -314,6 +314,31 @@ scfg: scfg@1570000 { compatible = "fsl,ls1046a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; big-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1570000 0x10000>; + + extirq: interrupt-controller@1ac { + compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1ac 4>; + interrupt-map = + <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xffffffff 0x0>; + }; }; crypto: crypto@1700000 { From c4a462485aee3de2c3b33395c0c88ba9526144d6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 30 Nov 2020 18:15:08 +0800 Subject: [PATCH 04/71] arm64: dts: ls1046ardb: Add interrupt line for RTC node Add interrupt line for RTC node, which is low level active. Signed-off-by: Hou Zhiqiang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index d53ccc56bb63..60acdf0b689e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019-2020 NXP * * Mingkai Hu */ @@ -74,6 +75,8 @@ &i2c3 { rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; + /* IRQ_RTC_B -> IRQ05, active low */ + interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>; }; }; From 0e88b5fd565da96375672ae547af5cdba46fdc0d Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 30 Nov 2020 18:15:09 +0800 Subject: [PATCH 05/71] arm64: dts: ls1088a: add DT node for external interrupt lines Add device-tree node for external interrupt lines IRQ0-IRQ11. Signed-off-by: Biwen Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 6403455ed039..ee0354928f6b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -220,6 +220,37 @@ dcfg: dcfg@1e00000 { little-endian; }; + isc: syscon@1f70000 { + compatible = "fsl,ls1088a-isc", "syscon"; + reg = <0x0 0x1f70000 0x0 0x10000>; + little-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1f70000 0x10000>; + + extirq: interrupt-controller@14 { + compatible = "fsl,ls1088a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x14 4>; + interrupt-map = + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xffffffff 0x0>; + }; + }; + tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; From 09b19ef878265e70e9b9cde283d41d66695e4cbe Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 30 Nov 2020 18:15:10 +0800 Subject: [PATCH 06/71] arm64: dts: ls1088ardb: fix interrupt line for RTC node Fix interrupt line for RTC node on ls1088ardb Signed-off-by: Biwen Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 528ec72d0b83..bf7b43ab1293 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -2,7 +2,7 @@ /* * Device Tree file for NXP LS1088A RDB Board. * - * Copyright 2017 NXP + * Copyright 2017-2020 NXP * * Harninder Rai * @@ -158,8 +158,8 @@ temp-sensor@4c { rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; - /* IRQ10_B */ - interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; + /* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU), active low */ + interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>; }; }; }; From ebb0713736ac98845178e81c0ae3ca3f2f11d3fb Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 30 Nov 2020 18:15:11 +0800 Subject: [PATCH 07/71] arm64: dts: ls208xa: add DT node for external interrupt lines Add device-tree node for external interrupt lines IRQ0-IRQ11. Signed-off-by: Biwen Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index c68901f8c6f0..767e3710bff2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -3,7 +3,7 @@ * Device Tree Include file for Freescale Layerscape-2080A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017-2020 NXP * * Abhimanyu Saini * @@ -277,6 +277,37 @@ dcfg: dcfg@1e00000 { little-endian; }; + isc: syscon@1f70000 { + compatible = "fsl,ls2080a-isc", "syscon"; + reg = <0x0 0x1f70000 0x0 0x10000>; + little-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1f70000 0x10000>; + + extirq: interrupt-controller@14 { + compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x14 4>; + interrupt-map = + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xffffffff 0x0>; + }; + }; + tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; From 6f5851a866b254b404cd7f50a24af0677a6b9fc3 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 30 Nov 2020 18:15:12 +0800 Subject: [PATCH 08/71] arm64: dts: ls208xa-rdb: add interrupt line for RTC node Add interrupt line for RTC node on ls208xa-rdb Signed-off-by: Biwen Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi index d0d670227ae2..4b71c4fcb35f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi @@ -3,7 +3,7 @@ * Device Tree file for Freescale LS2080A RDB Board. * * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017-2020 NXP * * Abhimanyu Saini * @@ -56,6 +56,8 @@ i2c@1 { rtc@68 { compatible = "dallas,ds3232"; reg = <0x68>; + /* IRQ_RTC_B -> IRQ06, active low */ + interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>; }; }; From 332b6a79b415e8b96b8dd87d4e8973192882d6a6 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 30 Nov 2020 18:15:13 +0800 Subject: [PATCH 09/71] arm64: dts: lx2160a: add DT node for external interrupt lines Add device-tree node for external interrupt lines IRQ0-IRQ11. Signed-off-by: Biwen Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 197397777c83..0d4bce13b8f1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -664,6 +664,37 @@ dcfg: syscon@1e00000 { little-endian; }; + isc: syscon@1f70000 { + compatible = "fsl,lx2160a-isc", "syscon"; + reg = <0x0 0x1f70000 0x0 0x10000>; + little-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1f70000 0x10000>; + + extirq: interrupt-controller@14 { + compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x14 4>; + interrupt-map = + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xffffffff 0x0>; + }; + }; + tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; From a430c3d2f0afd88466a0871bc876ec5246b8e09e Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 30 Nov 2020 18:15:14 +0800 Subject: [PATCH 10/71] arm64: dts: lx2160ardb: fix interrupt line for RTC node Fix interrupt line for RTC node on lx2160ardb Signed-off-by: Biwen Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 7723ad5efd37..eb88de7f3a9c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -2,7 +2,7 @@ // // Device Tree file for LX2160ARDB // -// Copyright 2018 NXP +// Copyright 2018-2020 NXP /dts-v1/; @@ -175,8 +175,8 @@ &i2c4 { rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; - // IRQ10_B - interrupts = <0 150 0x4>; + /* IRQ_RTC_B -> IRQ08, active low */ + interrupts-extended = <&extirq 8 IRQ_TYPE_LEVEL_LOW>; }; }; From 9c2eb8b7be78a0de6705ef543bd83514c56c6580 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 5 Jan 2021 11:32:59 +0800 Subject: [PATCH 11/71] arm64: dts: freescale: use fixed index mmcN for NXP layerscape reference boards The eSDHC driver has converted to use asynchronous probe. Let's use fixed index mmcN for eSDHC controllers, so that we can ignore the effect on usage, and avoid problem on previous use cases with fixed index mmcblkN. Signed-off-by: Yangbo Lu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 5 +++++ arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 5 +++++ arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 2 ++ 5 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts index 449475a97bf1..e22c5e77fecd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts @@ -13,6 +13,11 @@ / { model = "LS1012A QDS Board"; compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; + aliases { + mmc0 = &esdhc0; + mmc1 = &esdhc1; + }; + sys_mclk: clock-mclk { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts index d45c17620b98..f939d656898b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts @@ -12,6 +12,11 @@ / { model = "LS1012A RDB Board"; compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; + + aliases { + mmc0 = &esdhc0; + mmc1 = &esdhc1; + }; }; &duart0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index 2d1fe6c3797f..16ae3b00cf48 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -14,6 +14,8 @@ / { aliases { crypto = &crypto; + mmc0 = &esdhc0; + mmc1 = &esdhc1; serial0 = &uart0; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index eb88de7f3a9c..6f82759f0ce4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -14,6 +14,8 @@ / { aliases { crypto = &crypto; + mmc0 = &esdhc0; + mmc1 = &esdhc1; serial0 = &uart0; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index 91786848bd30..e1defee1ad27 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -14,6 +14,8 @@ / { aliases { crypto = &crypto; + mmc0 = &esdhc0; + mmc1 = &esdhc1; serial0 = &uart0; }; From 26442c799857d7b776085dde37fa93fc2fd21bd1 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 7 Dec 2020 17:12:34 +0800 Subject: [PATCH 12/71] arm64: dts: imx8mn: Configure clock rate for audio plls Configure clock rate for audio plls. audio pll1 is used as parent clock for clocks that is multiple of 8kHz. audio pll2 is used as parent clock for clocks that is multiple of 11kHz. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index ee1790230490..00808bb40680 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -581,7 +581,9 @@ clk: clock-controller@30380000 { <&clk IMX8MN_CLK_NOC>, <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, - <&clk IMX8MN_SYS_PLL3>; + <&clk IMX8MN_SYS_PLL3>, + <&clk IMX8MN_AUDIO_PLL1>, + <&clk IMX8MN_AUDIO_PLL2>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, <&clk IMX8MN_ARM_PLL_OUT>, <&clk IMX8MN_SYS_PLL3_OUT>, @@ -589,7 +591,9 @@ clk: clock-controller@30380000 { assigned-clock-rates = <0>, <0>, <0>, <400000000>, <400000000>, - <600000000>; + <600000000>, + <393216000>, + <361267200>; }; src: reset-controller@30390000 { From b5f2ace2283ce35df006d1f13ee9ea9dae3ba924 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 7 Dec 2020 17:12:35 +0800 Subject: [PATCH 13/71] arm64: dts: imx8mn-evk: Add sound-wm8524 card nodes Add sound-wm8524 card nodes which are supported on imx8mn-evk board. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 76d042a4cf09..1d2c399eabea 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -46,6 +46,32 @@ ir-receiver { pinctrl-0 = <&pinctrl_ir>; linux,autosuspend-period = <125>; }; + + wm8524: audio-codec { + #sound-dai-cells = <0>; + compatible = "wlf,wm8524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_wlf>; + wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + clock-names = "mclk"; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8524>; + audio-asrc = <&easrc>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; }; &fec1 { @@ -124,6 +150,16 @@ pca6416: gpio@20 { }; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -210,6 +246,12 @@ MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 >; }; + pinctrl_gpio_wlf: gpiowlfgrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 + >; + }; + pinctrl_ir: irgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f @@ -249,6 +291,15 @@ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 From 4c36eb101986f0719bf10ba14c44346ed85c3806 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 7 Dec 2020 17:12:36 +0800 Subject: [PATCH 14/71] arm64: dts: imx8mn-evk: Add sound-spdif card nodes Add sound-spdif card nodes which are supported on imx8mn-evk board. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 1d2c399eabea..a0dddba2e561 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -67,6 +67,14 @@ sound-wm8524 { "Line Out Jack", "LINEVOUTL", "Line Out Jack", "LINEVOUTR"; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; }; &easrc { @@ -164,6 +172,15 @@ &snvs_pwrkey { status = "okay"; }; +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -300,6 +317,13 @@ MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 >; }; + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 From edb93de429f97685f0793d4ad56ab3cbc630fa1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Thu, 17 Dec 2020 16:13:13 +0100 Subject: [PATCH 15/71] arm64: dts: imx8mq-librem5-devkit: Tweak pmic regulators MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BUCK3 needs a regulator-enable-ramp-delay since otherwise the board freezes on etnaviv probe. With this pgc_gpu suspends and resumes as expected. This must have been always broken since gpcv2 support was enabled. We also enable all the regulators needed for Deep Sleep Mode (DSM) as always-on: - VDD_SOC supplied by BUCK1 - VDDA_1P8 supplied by BUCK7 - VDDA_0P9 supplied by LDO4 - VDDA_DRAM supplied by LDO3 - NVCC_DRAM supplied by BUCK8 - VDD_DRAM supplied by BUCK5 Finally LDO5 and LDO6 provide VDD_PHY_1V8 and VDD_PHY_0V9 used by the SOCs MIPI, HDMI and USB IP cores. While we would in theory be able to turn these off (and I've tested that or LDO6 and mipi with USB disabled) it is of little practical use atm since USB doesn't runtime suspend so let's revisit this at a later point. Signed-off-by: Guido Günther Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5-devkit.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index af139b283daf..f35d6897fbf7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -298,6 +298,7 @@ buck1_reg: BUCK1 { regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; + regulator-always-on; regulator-ramp-delay = <1250>; rohm,dvs-run-voltage = <900000>; rohm,dvs-idle-voltage = <850000>; @@ -319,6 +320,7 @@ buck3_reg: BUCK3 { regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; + regulator-enable-ramp-delay = <200>; rohm,dvs-run-voltage = <900000>; }; @@ -334,6 +336,7 @@ buck5_reg: BUCK5 { regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; regulator-boot-on; + regulator-always-on; }; buck6_reg: BUCK6 { @@ -341,6 +344,7 @@ buck6_reg: BUCK6 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; regulator-boot-on; + regulator-always-on; }; buck7_reg: BUCK7 { @@ -348,6 +352,7 @@ buck7_reg: BUCK7 { regulator-min-microvolt = <1605000>; regulator-max-microvolt = <1995000>; regulator-boot-on; + regulator-always-on; }; buck8_reg: BUCK8 { @@ -355,6 +360,7 @@ buck8_reg: BUCK8 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-boot-on; + regulator-always-on; }; ldo1_reg: LDO1 { @@ -380,6 +386,7 @@ ldo3_reg: LDO3 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; + regulator-always-on; }; ldo4_reg: LDO4 { @@ -387,12 +394,14 @@ ldo4_reg: LDO4 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; + regulator-always-on; }; ldo5_reg: LDO5 { regulator-name = "ldo5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; ldo6_reg: LDO6 { @@ -400,6 +409,7 @@ ldo6_reg: LDO6 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; + regulator-always-on; }; ldo7_reg: LDO7 { @@ -407,6 +417,7 @@ ldo7_reg: LDO7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; + regulator-always-on; }; }; }; From ff38c1ddbb1cee7c87b186136c9591803b31aceb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Thu, 17 Dec 2020 16:13:14 +0100 Subject: [PATCH 16/71] arm64: dts: imx8mq-librem5-devkit: Disable snvs_rtc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The board has it's own RTC chip which is backed by the (optional) battery and hence preserves data/time on poweroff when that is inserted. Signed-off-by: Guido Günther Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index f35d6897fbf7..05a43ee6d051 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -897,6 +897,10 @@ &snvs_pwrkey { status = "okay"; }; +&snvs_rtc { + status = "disabled"; +}; + &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; From 48563c054f599d0fa29011eef7423dd0c67d1b55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Thu, 17 Dec 2020 16:13:15 +0100 Subject: [PATCH 17/71] arm64: dts: imx8mq-librem5-devkit: Drop custom clock settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Otherwise the boot hangs early on and the resulting clock tree without this already closely matches the selected rates (722534400 and 786432000). audio_pll2 0 0 0 722534397 0 0 50000 audio_pll2_bypass 0 0 0 722534397 0 0 50000 audio_pll2_out 0 0 0 722534397 0 0 50000 audio_pll1 1 1 0 786431998 0 0 50000 audio_pll1_bypass 1 1 0 786431998 0 0 50000 audio_pll1_out 1 1 0 786431998 0 0 50000 sai2 1 1 0 24576000 0 0 50000 sai2_root_clk 1 1 0 24576000 0 0 50000 sai6 0 0 0 24576000 0 0 50000 sai6_root_clk 0 0 0 24576000 0 0 50000 Signed-off-by: Guido Günther Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 05a43ee6d051..dd217a0760e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -244,11 +244,6 @@ &A53_3 { cpu-supply = <&buck2_reg>; }; -&clk { - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; - assigned-clock-rates = <786432000>, <722534400>; -}; - &dphy { status = "okay"; }; From 190621e0f6094001790b364900086448c1b12cf5 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 17 Dec 2020 11:25:29 -0600 Subject: [PATCH 18/71] arm64: dts: imx8mm-beacon: Drop unused clock-names reference The wlf,wm8962 driver does not use the clock-names property. Drop it. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index d6b9dedd168f..6f5e63696ec0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -102,7 +102,6 @@ wm8962: audio-codec@1a { compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - clock-names = "xclk"; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; From 62270eeb2b639ed840ee133e301073057d497ed8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Sun, 10 Jan 2021 17:55:51 +0100 Subject: [PATCH 19/71] arm64: dts: imx8mq: Add clock parents for mipi dphy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes sure the clock tree setup for the dphy is not dependent on other components. Without this change bringing up the display can fail like kernel: phy phy-30a00300.dphy.2: Invalid CM/CN/CO values: 165/217/1 kernel: phy phy-30a00300.dphy.2: for hs_clk/ref_clk=451656000/593999998 ~ 165/217 if LCDIF doesn't set up that part of the clock tree first. This was noticed when testing the Librem 5 devkit with defconfig. It doesn't happen when modules are built in. Signed-off-by: Guido Günther Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index a841a023e8e0..50ae17f65a51 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1016,9 +1016,14 @@ dphy: dphy@30a00300 { reg = <0x30a00300 0x100>; clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; clock-names = "phy_ref"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; #phy-cells = <0>; power-domains = <&pgc_mipi>; status = "disabled"; From 84b1f57d10679e4b20b0ddee001b03b062d8c90f Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Tue, 22 Dec 2020 16:13:44 +0100 Subject: [PATCH 20/71] arm64: dts: imx8mq-librem5: add vin-supply to VDD_1V8 buck7 is the supply here. Also, fix alphabetical ordering. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 64fc546b110f..55268fc0622e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -99,6 +99,14 @@ reg_vdd_sen: regulator-vdd-sen { regulator-max-microvolt = <3300000>; }; + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&buck7_reg>; + }; + reg_vdd_3v3: regulator-vdd-3v3 { compatible = "regulator-fixed"; regulator-name = "VDD_3V3"; @@ -106,13 +114,6 @@ reg_vdd_3v3: regulator-vdd-3v3 { regulator-max-microvolt = <3300000>; }; - reg_vdd_1v8: regulator-vdd-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - reg_vsys_3v4: regulator-vsys-3v4 { compatible = "regulator-fixed"; regulator-name = "VSYS_3V4"; From c003b15b4c102f9c34f4f77978c8d9b2707d7f53 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Tue, 22 Dec 2020 16:13:45 +0100 Subject: [PATCH 21/71] arm64: dts: imx8mq-librem5: add pinctrl for the touchscreen description In order for the touchscreen interrupt line to work, describe it properly. Otherwise it can work if defaults are ok, but we cannot be sure. Fixes: 8f0216b006e5 ("arm64: dts: Add a device tree for the Librem 5 phone") Signed-off-by: Martin Kepplinger Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 55268fc0622e..8fceecabd6b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -459,6 +459,13 @@ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 >; }; + pinctrl_touch: touchgrp { + fsl,pins = < + /* TP_INT */ + MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x80 + >; + }; + pinctrl_typec: typecgrp { fsl,pins = < /* TYPEC_MUX_EN */ @@ -880,6 +887,8 @@ led_backlight: led@0 { touchscreen@38 { compatible = "edt,edt-ft5506"; reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; interrupt-parent = <&gpio1>; interrupts = <27 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <720>; From 6a67d8fbee56c2e99cf71bddbd55ab1e39dd682a Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Tue, 22 Dec 2020 16:13:46 +0100 Subject: [PATCH 22/71] arm64: dts: imx8mq-librem5: Move usdhc clocks assignment to board DT According to commit e045f044e84e ("arm64: dts: imx8mq: Move usdhc clocks assignment to board DT") add the clocks assignment to imx8mq-librem5.dtsi too. Fixes: e045f044e84e ("arm64: dts: imx8mq: Move usdhc clocks assignment to board DT") Signed-off-by: Martin Kepplinger Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 8fceecabd6b4..f85d30a0c2cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1082,6 +1082,8 @@ mass-storage@1 { }; &usdhc1 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; + assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; @@ -1094,6 +1096,8 @@ &usdhc1 { }; &usdhc2 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; + assigned-clock-rates = <200000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>; From 1773b8d6697ac8e9380843fe5c13c25e95baa702 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Tue, 22 Dec 2020 16:13:47 +0100 Subject: [PATCH 23/71] arm64: dts: imx8mq-librem5-r3: workaround i2c1 issue with 1GHz cpu voltage This is a workaround for a hardware bug in the r3 revision that basically would stop the system due to traffic on the i2c1 bus. A cpu voltage change would trigger such traffic and that's what is avoided in order to work around it. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts index 6704ea2c72a3..0d38327043f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts @@ -10,6 +10,12 @@ / { compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; }; +&a53_opp_table { + opp-1000000000 { + opp-microvolt = <1000000>; + }; +}; + &accel_gyro { mount-matrix = "1", "0", "0", "0", "1", "0", From 70db442df67c79e8fc49e580e8a483aabc42ed3b Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 29 Dec 2020 12:47:34 +0100 Subject: [PATCH 24/71] arm64: dts: ls1012a: use constants in the clockgen phandle Now that we have constants, use them. This is just a mechanical change. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 60 +++++++++++++------ 1 file changed, 43 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 626b709d1fb9..7de6b376d792 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -7,6 +7,7 @@ * */ +#include #include #include @@ -34,7 +35,7 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; #cooling-cells = <2>; cpu-idle-states = <&CPU_PH20>; }; @@ -148,7 +149,10 @@ qspi: spi@1550000 { reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = ; clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 0>, <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; status = "disabled"; }; @@ -156,7 +160,8 @@ esdhc0: esdhc@1560000 { compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; interrupts = <0 62 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; big-endian; @@ -174,7 +179,8 @@ esdhc1: esdhc@1580000 { compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; reg = <0x0 0x1580000 0x0 0x10000>; interrupts = <0 65 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; big-endian; @@ -341,7 +347,8 @@ i2c0: i2c@2180000 { #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -351,7 +358,8 @@ i2c1: i2c@2190000 { #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -362,7 +370,8 @@ dspi: spi@2100000 { reg = <0x0 0x2100000 0x0 0x10000>; interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; spi-num-chipselects = <5>; big-endian; status = "disabled"; @@ -372,7 +381,8 @@ duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; status = "disabled"; }; @@ -380,7 +390,8 @@ duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; status = "disabled"; }; @@ -409,7 +420,7 @@ wdog0: watchdog@2ad0000 { "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; big-endian; }; @@ -418,8 +429,14 @@ sai1: sai@2b50000 { compatible = "fsl,vf610-sai"; reg = <0x0 0x2b50000 0x0 0x10000>; interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 47>, @@ -432,8 +449,14 @@ sai2: sai@2b60000 { compatible = "fsl,vf610-sai"; reg = <0x0 0x2b60000 0x0 0x10000>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 45>, @@ -453,8 +476,10 @@ edma0: edma@2c00000 { dma-channels = <32>; big-endian; clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 3>, - <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; }; usb0: usb@2f00000 { @@ -473,7 +498,8 @@ sata: sata@3200000 { <0x0 0x20140520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; dma-coherent; status = "disabled"; }; From 99314eb13c74b1b7cda73dcc3e779b9a5eb70e48 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 29 Dec 2020 12:47:35 +0100 Subject: [PATCH 25/71] arm64: dts: ls1028a: use constants in the clockgen phandle Now that we have constants, use them. This is just a mechanical change. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../fsl-ls1028a-kontron-sl28-var3-ads2.dts | 5 +- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 162 +++++++++++++----- 2 files changed, 120 insertions(+), 47 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts index c45d7b40e374..ed4e69e87e30 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts @@ -8,6 +8,8 @@ */ /dts-v1/; + +#include #include "fsl-ls1028a-kontron-sl28.dts" / { @@ -120,7 +122,8 @@ &soc { mclk: clock-mclk@f130080 { compatible = "fsl,vf610-sai-clock"; reg = <0x0 0xf130080 0x0 0x80>; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; #clock-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 60ff19fa53b4..401badb713c3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -8,6 +8,7 @@ * */ +#include #include #include @@ -30,7 +31,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a72"; reg = <0x0>; enable-method = "psci"; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -41,7 +42,7 @@ cpu1: cpu@1 { compatible = "arm,cortex-a72"; reg = <0x1>; enable-method = "psci"; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -235,7 +236,8 @@ i2c0: i2c@2000000 { #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -245,7 +247,8 @@ i2c1: i2c@2010000 { #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -255,7 +258,8 @@ i2c2: i2c@2020000 { #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -265,7 +269,8 @@ i2c3: i2c@2030000 { #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -275,7 +280,8 @@ i2c4: i2c@2040000 { #size-cells = <0>; reg = <0x0 0x2040000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -285,7 +291,8 @@ i2c5: i2c@2050000 { #size-cells = <0>; reg = <0x0 0x2050000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -295,7 +302,8 @@ i2c6: i2c@2060000 { #size-cells = <0>; reg = <0x0 0x2060000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -305,7 +313,8 @@ i2c7: i2c@2070000 { #size-cells = <0>; reg = <0x0 0x2070000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -317,7 +326,8 @@ fspi: spi@20c0000 { <0x0 0x20000000 0x0 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = ; - clocks = <&clockgen 2 0>, <&clockgen 2 0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 0>, + <&clockgen QORIQ_CLK_HWACCEL 0>; clock-names = "fspi_en", "fspi"; status = "disabled"; }; @@ -329,7 +339,8 @@ dspi0: spi@2100000 { reg = <0x0 0x2100000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; dmas = <&edma0 0 62>, <&edma0 0 60>; dma-names = "tx", "rx"; spi-num-chipselects = <4>; @@ -344,7 +355,8 @@ dspi1: spi@2110000 { reg = <0x0 0x2110000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; dmas = <&edma0 0 58>, <&edma0 0 56>; dma-names = "tx", "rx"; spi-num-chipselects = <4>; @@ -359,7 +371,8 @@ dspi2: spi@2120000 { reg = <0x0 0x2120000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; dmas = <&edma0 0 54>, <&edma0 0 2>; dma-names = "tx", "rx"; spi-num-chipselects = <3>; @@ -372,7 +385,7 @@ esdhc: mmc@2140000 { reg = <0x0 0x2140000 0x0 0x10000>; interrupts = ; clock-frequency = <0>; /* fixed up by bootloader */ - clocks = <&clockgen 2 1>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; little-endian; @@ -385,7 +398,7 @@ esdhc1: mmc@2150000 { reg = <0x0 0x2150000 0x0 0x10000>; interrupts = ; clock-frequency = <0>; /* fixed up by bootloader */ - clocks = <&clockgen 2 1>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; broken-cd; @@ -398,7 +411,8 @@ can0: can@2180000 { compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = ; - clocks = <&sysclk>, <&clockgen 4 1>; + clocks = <&sysclk>, <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -407,7 +421,8 @@ can1: can@2190000 { compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = ; - clocks = <&sysclk>, <&clockgen 4 1>; + clocks = <&sysclk>, <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -416,7 +431,8 @@ duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -424,7 +440,8 @@ duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -433,7 +450,8 @@ lpuart0: serial@2260000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2260000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; dma-names = "rx","tx"; dmas = <&edma0 1 32>, @@ -445,7 +463,8 @@ lpuart1: serial@2270000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2270000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; dma-names = "rx","tx"; dmas = <&edma0 1 30>, @@ -457,7 +476,8 @@ lpuart2: serial@2280000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2280000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; dma-names = "rx","tx"; dmas = <&edma0 1 28>, @@ -469,7 +489,8 @@ lpuart3: serial@2290000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2290000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; dma-names = "rx","tx"; dmas = <&edma0 1 26>, @@ -481,7 +502,8 @@ lpuart4: serial@22a0000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x22a0000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; dma-names = "rx","tx"; dmas = <&edma0 1 24>, @@ -493,7 +515,8 @@ lpuart5: serial@22b0000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x22b0000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; dma-names = "rx","tx"; dmas = <&edma0 1 22>, @@ -512,8 +535,10 @@ edma0: dma-controller@22c0000 { interrupt-names = "edma-tx", "edma-err"; dma-channels = <32>; clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 1>, - <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; }; gpio1: gpio@2300000 { @@ -575,7 +600,8 @@ sata: sata@3200000 { <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -747,14 +773,20 @@ qdma: dma-controller@8380000 { cluster1_core0_watchdog: watchdog@c000000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: watchdog@c010000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -763,8 +795,14 @@ sai1: audio-controller@f100000 { compatible = "fsl,vf610-sai"; reg = <0x0 0xf100000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 4>, @@ -778,8 +816,14 @@ sai2: audio-controller@f110000 { compatible = "fsl,vf610-sai"; reg = <0x0 0xf110000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 6>, @@ -793,8 +837,14 @@ sai3: audio-controller@f120000 { compatible = "fsl,vf610-sai"; reg = <0x0 0xf120000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 8>, @@ -808,8 +858,14 @@ sai4: audio-controller@f130000 { compatible = "fsl,vf610-sai"; reg = <0x0 0xf130000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 10>, @@ -823,8 +879,14 @@ sai5: audio-controller@f140000 { compatible = "fsl,vf610-sai"; reg = <0x0 0xf140000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 12>, @@ -838,8 +900,14 @@ sai6: audio-controller@f150000 { compatible = "fsl,vf610-sai"; reg = <0x0 0xf150000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 14>, @@ -960,7 +1028,7 @@ enetc_mdio_pf3: mdio@0,3 { ethernet@0,4 { compatible = "fsl,enetc-ptp"; reg = <0x000400 0 0 0 0>; - clocks = <&clockgen 2 3>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; little-endian; fsl,extts-fifo; }; @@ -1055,8 +1123,10 @@ malidp0: display@f080000 { interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, <0 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "DE", "SE"; - clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, - <&clockgen 2 2>; + clocks = <&dpclk>, + <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; arm,malidp-arqos-value = <0xd000d000>; From 7525022da260eac52e195d70bcd387056a53f8f0 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 29 Dec 2020 12:47:36 +0100 Subject: [PATCH 26/71] arm64: dts: ls1043a: use constants in the clockgen phandle Now that we have constants, use them. This is just a mechanical change. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 73 ++++++++++++------- .../boot/dts/freescale/qoriq-fman3-0.dtsi | 6 +- 2 files changed, 52 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 12bd1263158f..5a8a1dc4262d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -8,6 +8,7 @@ * Mingkai Hu */ +#include #include #include @@ -44,7 +45,7 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; @@ -54,7 +55,7 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; @@ -64,7 +65,7 @@ cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; @@ -74,7 +75,7 @@ cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; @@ -402,7 +403,10 @@ qspi: spi@1550000 { reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = <0 99 0x4>; clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 0>, <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; status = "disabled"; }; @@ -501,7 +505,8 @@ dspi0: spi@2100000 { reg = <0x0 0x2100000 0x0 0x10000>; interrupts = <0 64 0x4>; clock-names = "dspi"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; spi-num-chipselects = <5>; big-endian; status = "disabled"; @@ -514,7 +519,8 @@ dspi1: spi@2110000 { reg = <0x0 0x2110000 0x0 0x10000>; interrupts = <0 65 0x4>; clock-names = "dspi"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; spi-num-chipselects = <5>; big-endian; status = "disabled"; @@ -527,7 +533,8 @@ i2c0: i2c@2180000 { reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 0x4>; clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; dmas = <&edma0 1 39>, <&edma0 1 38>; dma-names = "tx", "rx"; @@ -541,7 +548,8 @@ i2c1: i2c@2190000 { reg = <0x0 0x2190000 0x0 0x10000>; interrupts = <0 57 0x4>; clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; status = "disabled"; }; @@ -552,7 +560,8 @@ i2c2: i2c@21a0000 { reg = <0x0 0x21a0000 0x0 0x10000>; interrupts = <0 58 0x4>; clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; status = "disabled"; }; @@ -563,7 +572,8 @@ i2c3: i2c@21b0000 { reg = <0x0 0x21b0000 0x0 0x10000>; interrupts = <0 59 0x4>; clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; status = "disabled"; }; @@ -571,28 +581,32 @@ duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; }; duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; }; duart2: serial@21d0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0500 0x0 0x100>; interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; }; duart3: serial@21d0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0600 0x0 0x100>; interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; }; gpio1: gpio@2300000 { @@ -704,7 +718,7 @@ lpuart0: serial@2950000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2950000 0x0 0x1000>; interrupts = <0 48 0x4>; - clocks = <&clockgen 0 0>; + clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; clock-names = "ipg"; status = "disabled"; }; @@ -713,7 +727,8 @@ lpuart1: serial@2960000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2960000 0x0 0x1000>; interrupts = <0 49 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; status = "disabled"; }; @@ -722,7 +737,8 @@ lpuart2: serial@2970000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2970000 0x0 0x1000>; interrupts = <0 50 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; status = "disabled"; }; @@ -731,7 +747,8 @@ lpuart3: serial@2980000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2980000 0x0 0x1000>; interrupts = <0 51 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; status = "disabled"; }; @@ -740,7 +757,8 @@ lpuart4: serial@2990000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2990000 0x0 0x1000>; interrupts = <0 52 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; status = "disabled"; }; @@ -749,7 +767,8 @@ lpuart5: serial@29a0000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x29a0000 0x0 0x1000>; interrupts = <0 53 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; status = "disabled"; }; @@ -758,7 +777,8 @@ wdog0: watchdog@2ad0000 { compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; interrupts = <0 83 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; clock-names = "wdog"; big-endian; }; @@ -775,8 +795,10 @@ edma0: edma@2c00000 { dma-channels = <32>; big-endian; clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 0>, - <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; }; usb0: usb@2f00000 { @@ -818,7 +840,8 @@ sata: sata@3200000 { <0x0 0x20140520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = <0 69 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; dma-coherent; }; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi index 4338db14c5da..ae1c2abaaf36 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi @@ -6,6 +6,8 @@ * */ +#include + fman0: fman@1a00000 { #address-cells = <1>; #size-cells = <1>; @@ -15,7 +17,7 @@ fman0: fman@1a00000 { reg = <0x0 0x1a00000 0x0 0xfe000>; interrupts = , ; - clocks = <&clockgen 3 0>; + clocks = <&clockgen QORIQ_CLK_FMAN 0>; clock-names = "fmanclk"; fsl,qman-channel-range = <0x800 0x10>; ptimer-handle = <&ptp_timer0>; @@ -81,6 +83,6 @@ ptp_timer0: ptp-timer@1afe000 { compatible = "fsl,fman-ptp-timer"; reg = <0x0 0x1afe000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 3 0>; + clocks = <&clockgen QORIQ_CLK_FMAN 0>; fsl,extts-fifo; }; From 973fb5e174b0d4c27d479abe1c632730c91e80cf Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 29 Dec 2020 12:47:37 +0100 Subject: [PATCH 27/71] arm64: dts: ls1046a: use constants in the clockgen phandle Now that we have constants, use them. This is just a mechanical change. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 73 ++++++++++++------- 1 file changed, 48 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index d3f5e48c58dd..f581a6d1f881 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -8,6 +8,7 @@ * Mingkai Hu */ +#include #include #include @@ -39,7 +40,7 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; @@ -49,7 +50,7 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x1>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; @@ -59,7 +60,7 @@ cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x2>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; @@ -69,7 +70,7 @@ cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x3>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; @@ -295,7 +296,10 @@ qspi: spi@1550000 { reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = ; clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -303,7 +307,7 @@ esdhc: esdhc@1560000 { compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 2 1>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; big-endian; @@ -479,7 +483,8 @@ dspi: spi@2100000 { reg = <0x0 0x2100000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; spi-num-chipselects = <5>; big-endian; status = "disabled"; @@ -491,7 +496,8 @@ i2c0: i2c@2180000 { #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; dmas = <&edma0 1 39>, <&edma0 1 38>; dma-names = "tx", "rx"; @@ -504,7 +510,8 @@ i2c1: i2c@2190000 { #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -514,7 +521,8 @@ i2c2: i2c@21a0000 { #size-cells = <0>; reg = <0x0 0x21a0000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -524,7 +532,8 @@ i2c3: i2c@21b0000 { #size-cells = <0>; reg = <0x0 0x21b0000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -532,7 +541,8 @@ duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -540,7 +550,8 @@ duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -548,7 +559,8 @@ duart2: serial@21d0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0500 0x0 0x100>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -556,7 +568,8 @@ duart3: serial@21d0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0600 0x0 0x100>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -604,7 +617,8 @@ lpuart0: serial@2950000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2950000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; status = "disabled"; }; @@ -613,7 +627,8 @@ lpuart1: serial@2960000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2960000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; status = "disabled"; }; @@ -622,7 +637,8 @@ lpuart2: serial@2970000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2970000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; status = "disabled"; }; @@ -631,7 +647,8 @@ lpuart3: serial@2980000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2980000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; status = "disabled"; }; @@ -640,7 +657,8 @@ lpuart4: serial@2990000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2990000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; status = "disabled"; }; @@ -649,7 +667,8 @@ lpuart5: serial@29a0000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x29a0000 0x0 0x1000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; status = "disabled"; }; @@ -658,7 +677,8 @@ wdog0: watchdog@2ad0000 { compatible = "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; big-endian; }; @@ -674,8 +694,10 @@ edma0: edma@2c00000 { dma-channels = <32>; big-endian; clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 1>, - <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; }; usb0: usb@2f00000 { @@ -714,7 +736,8 @@ sata: sata@3200000 { <0x0 0x20140520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; }; msi1: msi-controller@1580000 { From f9799323bda63d6d2e398caa413c0b242e311f83 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 29 Dec 2020 12:47:38 +0100 Subject: [PATCH 28/71] arm64: dts: ls1088a: use constants in the clockgen phandle Now that we have constants, use them. This is just a mechanical change. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 91 +++++++++++++------ 1 file changed, 64 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index ee0354928f6b..8ffbc9fde041 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -7,6 +7,7 @@ * Harninder Rai * */ +#include #include #include @@ -30,7 +31,7 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -39,7 +40,7 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -48,7 +49,7 @@ cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -57,7 +58,7 @@ cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -66,7 +67,7 @@ cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x100>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -75,7 +76,7 @@ cpu5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x101>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -84,7 +85,7 @@ cpu6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x102>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -93,7 +94,7 @@ cpu7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x103>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -310,7 +311,8 @@ dspi: spi@2100000 { reg = <0x0 0x2100000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; spi-num-chipselects = <6>; status = "disabled"; }; @@ -318,7 +320,8 @@ dspi: spi@2100000 { duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -326,7 +329,8 @@ duart0: serial@21c0500 { duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -391,7 +395,8 @@ i2c0: i2c@2000000 { #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; }; @@ -401,7 +406,8 @@ i2c1: i2c@2010000 { #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; }; @@ -411,7 +417,8 @@ i2c2: i2c@2020000 { #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; }; @@ -421,7 +428,8 @@ i2c3: i2c@2030000 { #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; }; @@ -434,7 +442,10 @@ qspi: spi@20c0000 { reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = ; clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -443,7 +454,7 @@ esdhc: esdhc@2140000 { reg = <0x0 0x2140000 0x0 0x10000>; interrupts = <0 28 0x4>; /* Level high type */ clock-frequency = <0>; - clocks = <&clockgen 2 1>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; little-endian; @@ -478,7 +489,8 @@ sata: sata@3200000 { <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; @@ -729,7 +741,8 @@ console@8340020 { ptp-timer@8b95000 { compatible = "fsl,dpaa2-ptp"; reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; little-endian; fsl,extts-fifo; }; @@ -818,56 +831,80 @@ pcs7_3: ethernet-phy@3 { cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: wdt@c010000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core2_watchdog: wdt@c020000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc020000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core3_watchdog: wdt@c030000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc030000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core0_watchdog: wdt@c100000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core1_watchdog: wdt@c110000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core2_watchdog: wdt@c120000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc120000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core3_watchdog: wdt@c130000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc130000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; From b0ccb208d76019362fd97d5463b848e1a6b2132d Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 29 Dec 2020 12:47:39 +0100 Subject: [PATCH 29/71] arm64: dts: ls208xa: use constants in the clockgen phandle Now that we have constants, use them. This is just a mechanical change. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 17 ++-- .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 17 ++-- .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 85 ++++++++++++++----- 3 files changed, 81 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index f9c1d30cf4a7..76ab68d2de0b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -9,6 +9,7 @@ * */ +#include #include "fsl-ls208xa.dtsi" &cpu { @@ -16,7 +17,7 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; #cooling-cells = <2>; @@ -26,7 +27,7 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x1>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; #cooling-cells = <2>; @@ -36,7 +37,7 @@ cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x100>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; #cooling-cells = <2>; @@ -46,7 +47,7 @@ cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x101>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; #cooling-cells = <2>; @@ -56,7 +57,7 @@ cpu4: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x200>; - clocks = <&clockgen 1 2>; + clocks = <&clockgen QORIQ_CLK_CMUX 2>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; #cooling-cells = <2>; @@ -66,7 +67,7 @@ cpu5: cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x201>; - clocks = <&clockgen 1 2>; + clocks = <&clockgen QORIQ_CLK_CMUX 2>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; #cooling-cells = <2>; @@ -76,7 +77,7 @@ cpu6: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x300>; - clocks = <&clockgen 1 3>; + clocks = <&clockgen QORIQ_CLK_CMUX 3>; next-level-cache = <&cluster3_l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -86,7 +87,7 @@ cpu7: cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x301>; - clocks = <&clockgen 1 3>; + clocks = <&clockgen QORIQ_CLK_CMUX 3>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; #cooling-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index a5f668d786b8..da24dc127698 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -9,6 +9,7 @@ * */ +#include #include "fsl-ls208xa.dtsi" &cpu { @@ -16,7 +17,7 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; #cooling-cells = <2>; @@ -26,7 +27,7 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x1>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; #cooling-cells = <2>; @@ -36,7 +37,7 @@ cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x100>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; #cooling-cells = <2>; @@ -46,7 +47,7 @@ cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x101>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; #cooling-cells = <2>; @@ -56,7 +57,7 @@ cpu4: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x200>; - clocks = <&clockgen 1 2>; + clocks = <&clockgen QORIQ_CLK_CMUX 2>; next-level-cache = <&cluster2_l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -66,7 +67,7 @@ cpu5: cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x201>; - clocks = <&clockgen 1 2>; + clocks = <&clockgen QORIQ_CLK_CMUX 2>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; #cooling-cells = <2>; @@ -76,7 +77,7 @@ cpu6: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x300>; - clocks = <&clockgen 1 3>; + clocks = <&clockgen QORIQ_CLK_CMUX 3>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; #cooling-cells = <2>; @@ -86,7 +87,7 @@ cpu7: cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x301>; - clocks = <&clockgen 1 3>; + clocks = <&clockgen QORIQ_CLK_CMUX 3>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; #cooling-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 767e3710bff2..135ac8210871 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -9,6 +9,7 @@ * */ +#include #include #include @@ -356,84 +357,112 @@ tmu: tmu@1f80000 { serial0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 0x4>; /* Level high type */ }; serial1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 0x4>; /* Level high type */ }; serial2: serial@21d0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0500 0x0 0x100>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 33 0x4>; /* Level high type */ }; serial3: serial@21d0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0600 0x0 0x100>; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 33 0x4>; /* Level high type */ }; cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: wdt@c010000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core0_watchdog: wdt@c100000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core1_watchdog: wdt@c110000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster3_core0_watchdog: wdt@c200000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc200000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster3_core1_watchdog: wdt@c210000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc210000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster4_core0_watchdog: wdt@c300000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc300000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster4_core1_watchdog: wdt@c310000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc310000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -484,7 +513,8 @@ console@8340020 { ptp-timer@8b95000 { compatible = "fsl,dpaa2-ptp"; reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; little-endian; fsl,extts-fifo; }; @@ -895,7 +925,8 @@ dspi: spi@2100000 { #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = <0 26 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "dspi"; spi-num-chipselects = <5>; bus-num = <0>; @@ -906,7 +937,8 @@ esdhc: esdhc@2140000 { compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; interrupts = <0 28 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; little-endian; @@ -965,7 +997,8 @@ i2c0: i2c@2000000 { reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; }; i2c1: i2c@2010000 { @@ -976,7 +1009,8 @@ i2c1: i2c@2010000 { reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; }; i2c2: i2c@2020000 { @@ -987,7 +1021,8 @@ i2c2: i2c@2020000 { reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; }; i2c3: i2c@2030000 { @@ -998,7 +1033,8 @@ i2c3: i2c@2030000 { reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ clock-names = "i2c"; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; }; ifc: ifc@2240000 { @@ -1022,7 +1058,10 @@ qspi: spi@20c0000 { <0x0 0x20000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "qspi_en", "qspi"; status = "disabled"; }; @@ -1120,7 +1159,8 @@ sata0: sata@3200000 { compatible = "fsl,ls2080a-ahci"; reg = <0x0 0x3200000 0x0 0x10000>; interrupts = <0 133 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; }; @@ -1129,7 +1169,8 @@ sata1: sata@3210000 { compatible = "fsl,ls2080a-ahci"; reg = <0x0 0x3210000 0x0 0x10000>; interrupts = <0 136 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; }; From 8e9f7797bcdfc95586bd9722e1944b1609d93fa6 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 29 Dec 2020 12:47:40 +0100 Subject: [PATCH 30/71] arm64: dts: lx2160a: use constants in the clockgen phandle Now that we have constants, use them. This is just a mechanical change. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 92 ++++++++++++------- 1 file changed, 57 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 0d4bce13b8f1..451e4430024c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -4,6 +4,7 @@ // // Copyright 2018-2020 NXP +#include #include #include #include @@ -30,7 +31,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x0>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -47,7 +48,7 @@ cpu1: cpu@1 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x1>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -64,7 +65,7 @@ cpu100: cpu@100 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x100>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -81,7 +82,7 @@ cpu101: cpu@101 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x101>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -98,7 +99,7 @@ cpu200: cpu@200 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x200>; - clocks = <&clockgen 1 2>; + clocks = <&clockgen QORIQ_CLK_CMUX 2>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -115,7 +116,7 @@ cpu201: cpu@201 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x201>; - clocks = <&clockgen 1 2>; + clocks = <&clockgen QORIQ_CLK_CMUX 2>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -132,7 +133,7 @@ cpu300: cpu@300 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x300>; - clocks = <&clockgen 1 3>; + clocks = <&clockgen QORIQ_CLK_CMUX 3>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -149,7 +150,7 @@ cpu301: cpu@301 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x301>; - clocks = <&clockgen 1 3>; + clocks = <&clockgen QORIQ_CLK_CMUX 3>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -166,7 +167,7 @@ cpu400: cpu@400 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x400>; - clocks = <&clockgen 1 4>; + clocks = <&clockgen QORIQ_CLK_CMUX 4>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -183,7 +184,7 @@ cpu401: cpu@401 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x401>; - clocks = <&clockgen 1 4>; + clocks = <&clockgen QORIQ_CLK_CMUX 4>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -200,7 +201,7 @@ cpu500: cpu@500 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x500>; - clocks = <&clockgen 1 5>; + clocks = <&clockgen QORIQ_CLK_CMUX 5>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -217,7 +218,7 @@ cpu501: cpu@501 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x501>; - clocks = <&clockgen 1 5>; + clocks = <&clockgen QORIQ_CLK_CMUX 5>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -234,7 +235,7 @@ cpu600: cpu@600 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x600>; - clocks = <&clockgen 1 6>; + clocks = <&clockgen QORIQ_CLK_CMUX 6>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -251,7 +252,7 @@ cpu601: cpu@601 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x601>; - clocks = <&clockgen 1 6>; + clocks = <&clockgen QORIQ_CLK_CMUX 6>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -268,7 +269,7 @@ cpu700: cpu@700 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x700>; - clocks = <&clockgen 1 7>; + clocks = <&clockgen QORIQ_CLK_CMUX 7>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -285,7 +286,7 @@ cpu701: cpu@701 { compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x701>; - clocks = <&clockgen 1 7>; + clocks = <&clockgen QORIQ_CLK_CMUX 7>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -716,7 +717,8 @@ i2c0: i2c@2000000 { reg = <0x0 0x2000000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -728,7 +730,8 @@ i2c1: i2c@2010000 { reg = <0x0 0x2010000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -739,7 +742,8 @@ i2c2: i2c@2020000 { reg = <0x0 0x2020000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -750,7 +754,8 @@ i2c3: i2c@2030000 { reg = <0x0 0x2030000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -761,7 +766,8 @@ i2c4: i2c@2040000 { reg = <0x0 0x2040000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -773,7 +779,8 @@ i2c5: i2c@2050000 { reg = <0x0 0x2050000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -784,7 +791,8 @@ i2c6: i2c@2060000 { reg = <0x0 0x2060000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -795,7 +803,8 @@ i2c7: i2c@2070000 { reg = <0x0 0x2070000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -807,7 +816,10 @@ fspi: spi@20c0000 { <0x0 0x20000000 0x0 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "fspi_en", "fspi"; status = "disabled"; }; @@ -818,7 +830,8 @@ dspi0: spi@2100000 { #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; clock-names = "dspi"; spi-num-chipselects = <5>; bus-num = <0>; @@ -831,7 +844,8 @@ dspi1: spi@2110000 { #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; clock-names = "dspi"; spi-num-chipselects = <5>; bus-num = <1>; @@ -844,7 +858,8 @@ dspi2: spi@2120000 { #size-cells = <0>; reg = <0x0 0x2120000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; clock-names = "dspi"; spi-num-chipselects = <5>; bus-num = <2>; @@ -855,7 +870,8 @@ esdhc0: esdhc@2140000 { compatible = "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; interrupts = <0 28 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; dma-coherent; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; @@ -868,7 +884,8 @@ esdhc1: esdhc@2150000 { compatible = "fsl,esdhc"; reg = <0x0 0x2150000 0x0 0x10000>; interrupts = <0 63 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; dma-coherent; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; @@ -1004,7 +1021,8 @@ sata0: sata@3200000 { <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; @@ -1015,7 +1033,8 @@ sata1: sata@3210000 { <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; @@ -1026,7 +1045,8 @@ sata2: sata@3220000 { <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; @@ -1037,7 +1057,8 @@ sata3: sata@3230000 { <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; @@ -1310,7 +1331,8 @@ console@8340020 { ptp-timer@8b95000 { compatible = "fsl,dpaa2-ptp"; reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; little-endian; fsl,extts-fifo; }; From ce58459d8c7f4174e7b8a8ea903dd949631334a3 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Mon, 4 Jan 2021 17:15:42 +0800 Subject: [PATCH 31/71] arm64: dts: imx8m: add SoC ID compatible Add compatible string to .dtsi files for binding of imx8_soc_info and device. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alice Guo Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c824f2615fe8..d457ce815e68 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -257,7 +257,7 @@ usbphynop2: usbphynop2 { }; soc@0 { - compatible = "simple-bus"; + compatible = "fsl,imx8mm-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 00808bb40680..e96fd9a24e0e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -241,7 +241,7 @@ timer { }; soc@0 { - compatible = "simple-bus"; + compatible = "fsl,imx8mn-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ecccfbb4f5ad..ec6ac523ecfc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -218,7 +218,7 @@ timer { }; soc@0 { - compatible = "simple-bus"; + compatible = "fsl,imx8mp-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 50ae17f65a51..64398599591b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -286,7 +286,7 @@ timer { }; soc@0 { - compatible = "simple-bus"; + compatible = "fsl,imx8mq-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; From cbff23797fa1ec00e3bdda57d8472f75c0b7aab9 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Mon, 4 Jan 2021 17:15:43 +0800 Subject: [PATCH 32/71] arm64: dts: imx8m: add NVMEM provider and consumer to read soc unique ID In order to be able to use NVMEM APIs to read soc unique ID, add the nvmem data cell and name for nvmem-cells to the "soc" node, and add a nvmem node which provides soc unique ID to efuse@30350000. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alice Guo Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index d457ce815e68..9bee6f1889a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -261,6 +261,8 @@ soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mm_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -518,6 +520,10 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; + imx8mm_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index e96fd9a24e0e..d021aba5fb1f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -245,6 +245,8 @@ soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mn_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -531,6 +533,10 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; + imx8mn_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ec6ac523ecfc..9401e92f1c84 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -222,6 +222,8 @@ soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mp_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -328,6 +330,10 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; + imx8mp_uid: unique-id@420 { + reg = <0x8 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 64398599591b..9fcb001b8dde 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -291,6 +291,8 @@ soc@0 { #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + nvmem-cells = <&imx8mq_uid>; + nvmem-cell-names = "soc_unique_id"; bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; @@ -555,6 +557,10 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; + imx8mq_uid: soc-uid@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; From 6f30b27c5ef54a266d188ffbee3bacfdd40e8f73 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 4 Jan 2021 09:36:47 -0800 Subject: [PATCH 33/71] arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits The Gateworks Venice GW71xx-0x/GW72xx-0x/GW73xx-0x are development kits consisting of a GW700x SoM and a Baseboard. Future SoM's such as the GW701x will create additional combinations. The GW700x SoM contains: - i.MX 8M Mini SoC - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller (eeprom/pushbutton/reset/voltage-monitor) - GbE PHY connected to the i.MX 8M Mini FEC - Power Management IC The GW71xx Baseboard contains: - 1x MiniPCIe Socket with USB2.0, PCIe, and SIM - 1x RJ45 GbE (i.MX 8M Mini FEC) - I/O connector with 1x-SPI/1x-I2C/1x-UART/4x-GPIO signals - PCIe Clock generator - GPS and accelerometer - 1x USB 2.0 Front Panel connector - wide range power supply The GW72xx Baseboard contains: - 2x MiniPCIe Socket with USB2.0, PCIe, and SIM - 2x RJ45 GbE (i.MX 8M Mini FEC and LAN743x) - 1x MicroSD connector - 1x USB 2.0 Front Panel connector - 1x SPI connector - 1x Serial connector supporting 2x-UART or 1x-UART configured as 1 of: RS232 w/ flow-control, RS485, RS422 - PCIe Clock generator - GPS and accelerometer - Media Expansion connector (MIPI-CSI/MIPI-DSI/GPIO/I2S) - I/O connector with 2x-ADC,2x-GPIO,1x-UART,1x-I2C - wide range power supply The GW73xx Baseboard contains: - 3x MiniPCIe Socket with USB2.0, PCIe, and SIM - 2x RJ45 GbE (i.MX 8M Mini FEC and LAN743x) - 1x MicroSD connector - 1x USB 2.0 Front Panel connector - 1x SPI connector - 1x Serial connector supporting 2x-UART or 1x-UART configured as 1 of: RS232 w/ flow-control, RS485, RS422 - WiFi/BT - PCIe Clock generator - GPS and accelerometer - Media Expansion connector (MIPI-CSI/MIPI-DSI/GPIO/I2S) - I/O connector with 2x-ADC,2x-GPIO,1x-UART,1x-I2C - wide range power supply Signed-off-by: Tim Harvey Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 3 + .../dts/freescale/imx8mm-venice-gw700x.dtsi | 495 ++++++++++++++++++ .../dts/freescale/imx8mm-venice-gw71xx-0x.dts | 19 + .../dts/freescale/imx8mm-venice-gw71xx.dtsi | 186 +++++++ .../dts/freescale/imx8mm-venice-gw72xx-0x.dts | 20 + .../dts/freescale/imx8mm-venice-gw72xx.dtsi | 311 +++++++++++ .../dts/freescale/imx8mm-venice-gw73xx-0x.dts | 19 + .../dts/freescale/imx8mm-venice-gw73xx.dtsi | 362 +++++++++++++ 8 files changed, 1415 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 901d80086b47..6f76026a2c3c 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -34,6 +34,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi new file mode 100644 index 000000000000..c769fadbd008 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Gateworks Corporation + */ + +#include +#include +#include + +/ { + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck3_reg>; +}; + +&A53_1 { + cpu-supply = <&buck3_reg>; +}; + +&A53_2 { + cpu-supply = <&buck3_reg>; +}; + +&A53_3 { + cpu-supply = <&buck3_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + tx-fifo-depth = ; + rx-fifo-depth = ; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@16 { + gw,mode = <4>; + reg = <0x16>; + label = "fan_tach"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_adc1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_adc2"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_dram"; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_1p2"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_1p0"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_0p95"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p8"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + + fan-controller@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "gw,gsc-fan"; + reg = <0x0a>; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; + + pmic@69 { + compatible = "mps,mp5416"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x69>; + + regulators { + buck1 { + regulator-name = "vdd_0p95"; + regulator-min-microvolt = <805000>; + regulator-max-microvolt = <1000000>; + regulator-max-microamp = <2500000>; + regulator-boot-on; + }; + + buck2 { + regulator-name = "vdd_soc"; + regulator-min-microvolt = <805000>; + regulator-max-microvolt = <900000>; + regulator-max-microamp = <1000000>; + regulator-boot-on; + }; + + buck3_reg: buck3 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <805000>; + regulator-max-microvolt = <1000000>; + regulator-max-microamp = <2200000>; + regulator-boot-on; + }; + + buck4 { + regulator-name = "vdd_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-max-microamp = <500000>; + regulator-boot-on; + }; + + ldo1 { + regulator-name = "nvcc_snvs_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-max-microamp = <300000>; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "vdd_snvs_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "vdd_0p95"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + }; + + ldo4 { + regulator-name = "vdd_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts new file mode 100644 index 000000000000..3f88c4ad5716 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mm.dtsi" +#include "imx8mm-venice-gw700x.dtsi" +#include "imx8mm-venice-gw71xx.dtsi" + +/ { + model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit"; + compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi new file mode 100644 index 000000000000..905b68a3daa5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Gateworks Corporation + */ + +#include +#include + +/ { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 + >; + }; + + pinctrl_reg_usb1_en: regusb1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts new file mode 100644 index 000000000000..b1e7540f0281 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mm.dtsi" +#include "imx8mm-venice-gw700x.dtsi" +#include "imx8mm-venice-gw72xx.dtsi" + +/ { + model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit"; + compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi new file mode 100644 index 000000000000..b7c91bdc21dd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Gateworks Corporation + */ + +#include +#include + +/ { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* off-board header */ +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* RS232 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 + >; + }; + + pinctrl_reg_usb1_en: regusb1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts new file mode 100644 index 000000000000..6905437ff281 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mm.dtsi" +#include "imx8mm-venice-gw700x.dtsi" +#include "imx8mm-venice-gw73xx.dtsi" + +/ { + model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit"; + compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi new file mode 100644 index 000000000000..d2ffd62a3bd4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Gateworks Corporation + */ + +#include +#include + +/ { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_wifi_en: regulator-wifi-en { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wl>; + compatible = "regulator-fixed"; + regulator-name = "wl"; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* off-board header */ +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* bluetooth HCI */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; + cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; +}; + +/* RS232 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 + >; + }; + + pinctrl_bten: btengrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 + >; + }; + + pinctrl_reg_wl: regwlgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + >; + }; + + pinctrl_reg_usb1_en: regusb1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; From 88f7f6bcca371b71ba93ff9c170c7c87927654df Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Thu, 7 Jan 2021 10:12:11 +0100 Subject: [PATCH 34/71] arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP Add initial support for phyBOARD-Pollux-i.MX8MP. Supported basic features: * eMMC * i2c EEPROM * i2c RTC * i2c LED * PMIC * debug UART * SD card * 1Gbit Ethernet (fec) * watchdog Signed-off-by: Teresa Remmet Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mp-phyboard-pollux-rdk.dts | 161 ++++++++++ .../dts/freescale/imx8mp-phycore-som.dtsi | 293 ++++++++++++++++++ 3 files changed, 455 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 6f76026a2c3c..38559943c15d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts new file mode 100644 index 000000000000..0e1a6d953389 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; + +#include +#include +#include "imx8mp-phycore-som.dtsi" + +/ { + model = "PHYTEC phyBOARD-Pollux i.MX8MP"; + compatible = "phytec,imx8mp-phyboard-pollux-rdk", + "phytec,imx8mp-phycore-som", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + leds@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led1 { + type = ; + }; + + led2 { + type = ; + }; + + led3 { + type = ; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* debug console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2_pins: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi new file mode 100644 index 000000000000..44a8c2337cee --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include +#include "imx8mp.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX8MP"; + compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; + + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +/* ethernet 1 */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,clk-output-sel = ; + enet-phy-lane-no-swap; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-compatible = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-compatible = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-compatible = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-compatible = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-compatible = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-compatible = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-compatible = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-compatible = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-compatible = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-compatible = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + trickle-resistor-ohms = <3000>; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; From 642856097c186c0d675a8ac59efca557e8d9c0eb Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 11 Jan 2021 09:21:34 +0100 Subject: [PATCH 35/71] arm64: dts: freescale: sl28: add variant 1 There is a new variant 1 of this board available. It features up to four SerDes lanes for customer use. Add a new device tree which features just the basic peripherals. A customer will then have to modify or append to this device tree. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../fsl-ls1028a-kontron-sl28-var1.dts | 62 +++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 38559943c15d..17fc731da700 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts new file mode 100644 index 000000000000..6c309b97587d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 1 which has one ethernet port. It is + * different than the base variant, which also has one port, but here the + * port is connected via RGMII. This port is not TSN aware. + * None of the four SerDes lanes are used by the module, instead they are + * all led out to the carrier for customer use. + * + * Copyright (C) 2020 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" +#include + +/ { + model = "Kontron SMARC-sAL28 (4 Lanes)"; + compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; +}; + +&enetc_port0 { + status = "disabled"; + /* + * Delete both the phy-handle to the old phy0 label as well as + * the mdio node with the old phy node with the old phy0 label. + */ + /delete-property/ phy-handle; + /delete-node/ mdio; +}; + +&enetc_port1 { + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = ; + vddio-supply = <&vddh>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; + }; +}; From f18e6d573b80364bc6be71cd32d5eb92543a99c1 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Thu, 7 Jan 2021 13:17:50 +0100 Subject: [PATCH 36/71] arm64: dts: imx8mq: Add NOC node Add initial support for dynamic frequency scaling of the main NOC on imx8mq. Make DDRC the parent of the NOC (using passive governor) so that the main NOC is automatically scaled together with DDRC by default. Support for proactive scaling via interconnect will come on top. Signed-off-by: Leonard Crestez Signed-off-by: Martin Kepplinger Acked-by: Georgi Djakov Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9fcb001b8dde..efabd7bb88cf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1169,6 +1169,30 @@ fec1: ethernet@30be0000 { }; }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MQ_CLK_NOC>; + fsl,ddrc = <&ddrc>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + + opp-400M { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + bus@32c00000 { /* AIPS4 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; From 20cf8d981c8164367cbccfabbd306b7c9f7ad1ed Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Mon, 11 Jan 2021 09:21:44 +0100 Subject: [PATCH 37/71] arm64: dts: imx8mq: Add interconnect provider property Add #interconnect-cells on main &noc so that it will probe the interconnect provider. Signed-off-by: Martin Kepplinger Acked-by: Georgi Djakov Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index efabd7bb88cf..02b22faa8147 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1174,6 +1174,7 @@ noc: interconnect@32700000 { reg = <0x32700000 0x100000>; clocks = <&clk IMX8MQ_CLK_NOC>; fsl,ddrc = <&ddrc>; + #interconnect-cells = <1>; operating-points-v2 = <&noc_opp_table>; noc_opp_table: opp-table { From ad1abc8a03fdbc05b3390962b15287d4e7c5db22 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 7 Jan 2021 13:17:53 +0100 Subject: [PATCH 38/71] arm64: dts: imx8mq: Add interconnect for lcdif Add interconnect ports for lcdif to set bus capabilities. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 02b22faa8147..c9874dfe0cd4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -11,6 +11,7 @@ #include "dt-bindings/input/input.h" #include #include +#include #include "imx8mq-pinfunc.h" / { @@ -524,6 +525,8 @@ lcdif: lcd-controller@30320000 { <&clk IMX8MQ_VIDEO_PLL1>, <&clk IMX8MQ_VIDEO_PLL1_OUT>; assigned-clock-rates = <0>, <0>, <0>, <594000000>; + interconnects = <&noc IMX8MQ_ICM_LCDIF &noc IMX8MQ_ICS_DRAM>; + interconnect-names = "dram"; status = "disabled"; port@0 { From 8900d0d59b63766c4ed10462eb921c4bd595e4c7 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 8 Jan 2021 23:09:58 +0000 Subject: [PATCH 39/71] arm64: dts: lx2160a-clearfog-itx: add power button support Add support for the power button. Signed-off-by: Russell King Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index f3741a32e868..2b63235ca627 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -8,6 +8,7 @@ /dts-v1/; #include "fsl-lx2160a-cex7.dtsi" +#include / { aliases { @@ -18,6 +19,17 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + gpio-keys { + compatible = "gpio-keys"; + + key { + label = "power"; + linux,can-disable; + linux,code = ; + gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + }; + }; }; &emdio2 { From e8d08d80f4508e0601ea2beb0848b5a60d6a2c31 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Jan 2021 05:38:26 -0600 Subject: [PATCH 40/71] arm64: dts: imx8mm-beacon: add more pinctrl states for usdhc1 The WiFi chip is capable of communication at SDR104 speeds. Enable 100Mhz and 200MHz pinmux to support this. Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index d897913537ca..988f8ab679ad 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -256,8 +256,10 @@ bluetooth { &usdhc1 { #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <4>; non-removable; cap-power-off-card; From 18b9de73f06e474456699bd743a054de9b905706 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Jan 2021 05:53:53 -0600 Subject: [PATCH 41/71] arm64: dts: imx8mn-beacon-som: Configure RTC aliases On the i.MX8MN Beacon SOM, there is an RTC chip which is fed power from the baseboard during power off. The SNVS RTC integrated into the SoC is not fed power. Depending on the order the modules are loaded, this can be a problem if the external RTC isn't rtc0. Make the alias for rtc0 point to the external RTC all the time and rtc1 point to the SVNS in order to correctly hold date/time over a power-cycle. Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 67e5e5b9ddea..2120e6485393 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -4,6 +4,11 @@ */ / { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -212,7 +217,7 @@ eeprom@50 { reg = <0x50>; }; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; }; From 12dffe14e372ab7af26c12ca4cc91876a0fb7b41 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 10 Jan 2021 13:58:15 +0000 Subject: [PATCH 42/71] arm64: dts: lx2160a-cex7: delete RTC interrupt The RTC interrupt is incorrect and prevents the RTC driver initialising. In any case, the PCF2127 driver wants an active low interrupt, which neither the GIC nor the GPIO blocks support. There is an ISPPT block in the LX2160A, but this is not supported in mainline kernels. So, just delete the interrupt. Signed-off-by: Russell King Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index d87d16460875..49fcf025494f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -134,8 +134,6 @@ &i2c4 { rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; - // IRQ10_B - interrupts = ; }; }; From 5dd74cf8f3e68fa46a253804ac42e9d3f4f58885 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 10 Jan 2021 20:54:54 +0100 Subject: [PATCH 43/71] arm64: dts: freescale: sl28: enable SATA support With a newer bootloader SATA might be used in a mPCI slot using a mSATA card. Enable the SATA controller on the Kontron K-Box LS-230-A which comes with such a slot. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts index d66d8b2c3d1a..6b575efd84a7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts @@ -107,3 +107,7 @@ &mscc_felix_port4 { ethernet = <&enetc_port2>; status = "okay"; }; + +&sata { + status = "okay"; +}; From 8b6b17540370415889fb1a7170bc8c4dba18edd6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 8 Jan 2021 09:47:26 -0300 Subject: [PATCH 44/71] arm64: dts: imx8mq: Add eCSPI DMA support eCSPI ports have DMA capability. Describe the eCSPI DMA properties. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c9874dfe0cd4..4ef8c92403dd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -835,6 +835,8 @@ ecspi1: spi@30820000 { clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, <&clk IMX8MQ_CLK_ECSPI1_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -847,6 +849,8 @@ ecspi2: spi@30830000 { clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, <&clk IMX8MQ_CLK_ECSPI2_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -859,6 +863,8 @@ ecspi3: spi@30840000 { clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, <&clk IMX8MQ_CLK_ECSPI3_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; From 69c910d3675fc44ed8e387c816afb79d54371314 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 11 Jan 2021 12:45:55 +0100 Subject: [PATCH 45/71] arm64: dts: ls1028a: fix FlexSPI clock Now that we have a proper driver for the FlexSPI interface use it. This will fix SCK frequency switching on Layerscape SoCs. This was tested on the Kontron sl28 board. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 401badb713c3..045739dbcb17 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -206,9 +206,20 @@ ddr: memory-controller@1080000 { }; dcfg: syscon@1e00000 { - compatible = "fsl,ls1028a-dcfg", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; reg = <0x0 0x1e00000 0x0 0x10000>; + ranges = <0x0 0x0 0x1e00000 0x10000>; little-endian; + + fspi_clk: clock-controller@900 { + compatible = "fsl,ls1028a-flexspi-clk"; + reg = <0x900 0x4>; + #clock-cells = <0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; + clock-output-names = "fspi_clk"; + }; }; rst: syscon@1e60000 { @@ -326,8 +337,7 @@ fspi: spi@20c0000 { <0x0 0x20000000 0x0 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = ; - clocks = <&clockgen QORIQ_CLK_HWACCEL 0>, - <&clockgen QORIQ_CLK_HWACCEL 0>; + clocks = <&fspi_clk>, <&fspi_clk>; clock-names = "fspi_en", "fspi"; status = "disabled"; }; From 70eacf42a93aff6589a8b91279bbfe5f73c4ca3d Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Sat, 16 Jan 2021 16:44:28 +0800 Subject: [PATCH 46/71] arm64: dts: imx8m: correct assigned clocks for FEC CLK_ENET_TIMER assigned clocks twice, should be a typo, correct to CLK_ENET_PHY_REF clock. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 7 ++++--- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 7 ++++--- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 ++++--- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 9bee6f1889a4..5af0e63b1db1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -915,11 +915,12 @@ fec1: ethernet@30be0000 { assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, <&clk IMX8MM_CLK_ENET_TIMER>, <&clk IMX8MM_CLK_ENET_REF>, - <&clk IMX8MM_CLK_ENET_TIMER>; + <&clk IMX8MM_CLK_ENET_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, <&clk IMX8MM_SYS_PLL2_100M>, - <&clk IMX8MM_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + <&clk IMX8MM_SYS_PLL2_125M>, + <&clk IMX8MM_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index d021aba5fb1f..79c389969b83 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -913,11 +913,12 @@ fec1: ethernet@30be0000 { assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, <&clk IMX8MN_CLK_ENET_TIMER>, <&clk IMX8MN_CLK_ENET_REF>, - <&clk IMX8MN_CLK_ENET_TIMER>; + <&clk IMX8MN_CLK_ENET_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, <&clk IMX8MN_SYS_PLL2_100M>, - <&clk IMX8MN_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + <&clk IMX8MN_SYS_PLL2_125M>, + <&clk IMX8MN_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9401e92f1c84..ba32725ff28c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -768,11 +768,12 @@ fec: ethernet@30be0000 { assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, <&clk IMX8MP_CLK_ENET_TIMER>, <&clk IMX8MP_CLK_ENET_REF>, - <&clk IMX8MP_CLK_ENET_TIMER>; + <&clk IMX8MP_CLK_ENET_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, <&clk IMX8MP_SYS_PLL2_100M>, - <&clk IMX8MP_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + <&clk IMX8MP_SYS_PLL2_125M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; status = "disabled"; From 6c17f2d6ab50691bfe67e65434568d759feb450b Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Sat, 16 Jan 2021 16:44:29 +0800 Subject: [PATCH 47/71] arm64: dts: imx8mq: assign clock parents for FEC Assign clock parents for FEC, set "ptp" clock to 100M, "enet_clk_ref" to 125M. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 4ef8c92403dd..adcd6d5f6f5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1172,6 +1172,15 @@ fec1: ethernet@30be0000 { <&clk IMX8MQ_CLK_ENET_PHY_REF>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, + <&clk IMX8MQ_CLK_ENET_TIMER>, + <&clk IMX8MQ_CLK_ENET_REF>, + <&clk IMX8MQ_CLK_ENET_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_125M>, + <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; status = "disabled"; From 066438ae637b492f220c26cca304f1ce3d987a20 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Sat, 16 Jan 2021 16:44:30 +0800 Subject: [PATCH 48/71] arm64: dts: imx8m: add mac address for FEC Add mac address in efuse, so that FEC driver can parse it from nvmem cell. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 7 +++++++ 4 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 5af0e63b1db1..acb8df609e2b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -527,6 +527,10 @@ imx8mm_uid: unique-id@410 { cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@90 { + reg = <0x90 6>; + }; }; anatop: anatop@30360000 { @@ -923,6 +927,9 @@ fec1: ethernet@30be0000 { assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 79c389969b83..fae95114fd0a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -540,6 +540,10 @@ imx8mn_uid: unique-id@410 { cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@90 { + reg = <0x90 6>; + }; }; anatop: anatop@30360000 { @@ -921,6 +925,9 @@ fec1: ethernet@30be0000 { assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ba32725ff28c..9dc63eddce16 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -337,6 +337,10 @@ imx8mp_uid: unique-id@420 { cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + eth_mac1: mac-address@90 { + reg = <0x90 6>; + }; }; anatop: anatop@30360000 { @@ -776,6 +780,9 @@ fec: ethernet@30be0000 { assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index adcd6d5f6f5f..a0ca7fc4b220 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -567,6 +567,10 @@ imx8mq_uid: soc-uid@410 { cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@90 { + reg = <0x90 6>; + }; }; anatop: syscon@30360000 { @@ -1183,6 +1187,9 @@ fec1: ethernet@30be0000 { assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; status = "disabled"; }; }; From afe993546334633daa3249b77540a30c0fb8997e Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Sat, 16 Jan 2021 16:44:31 +0800 Subject: [PATCH 49/71] arm64: dts: imx8m: add fsl,stop-mode property for FEC Add fsl,stop-mode property for FEC to enable stop mode. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index acb8df609e2b..6bf1d15ba16a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -930,6 +930,7 @@ fec1: ethernet@30be0000 { nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; nvmem_macaddr_swap; + fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index fae95114fd0a..8004b7f36c77 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -928,6 +928,7 @@ fec1: ethernet@30be0000 { nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; nvmem_macaddr_swap; + fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9dc63eddce16..47c8fe10a5ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -782,6 +782,7 @@ fec: ethernet@30be0000 { fsl,num-rx-queues = <3>; nvmem-cells = <ð_mac1>; nvmem-cell-names = "mac-address"; + fsl,stop-mode = <&gpr 0x10 3>; nvmem_macaddr_swap; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index a0ca7fc4b220..963c97b4ba84 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1190,6 +1190,7 @@ fec1: ethernet@30be0000 { nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; nvmem_macaddr_swap; + fsl,stop-mode = <&iomuxc_gpr 0x10 3>; status = "disabled"; }; }; From c0b70f05c87f3b09b391027c6f056d0facf331ef Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 15 Jan 2021 11:26:57 +0800 Subject: [PATCH 50/71] arm64: dts: imx8mq: use_dt_domains for pci node We are using Jailhouse Hypervsior which has virtual pci node that use dt domains. so also use dt domains for pci node, this will avoid conflict with Jailhouse Hypervisor to trigger the following error: pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); Reviewed-by: Richard Zhu Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 963c97b4ba84..17c449e12c2e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1377,6 +1377,7 @@ pcie0: pcie@33800000 { <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; + linux,pci-domain = <0>; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, @@ -1406,6 +1407,7 @@ pcie1: pcie@33c00000 { <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; + linux,pci-domain = <1>; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, From 22171213e503edce38f249cff82b9ad3775b9026 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 15 Jan 2021 23:36:39 +0000 Subject: [PATCH 51/71] arm64: dts: lx2160a-cex7: increase at8035 PHY gigabit Tw parameter Increase the SmartEEE Tw parameter for Atheros PHYs to stop gigabit links from sporadically dropping. Testing on this platform shows that a value of 24 results in a stable link, whereas 23 or below has the occasional drop. Tested with a Netgear GS116 unmanaged switch link partner with Cat 5e cabling. Signed-off-by: Russell King Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index 49fcf025494f..459dccad8326 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -40,6 +40,7 @@ &emdio1 { rgmii_phy1: ethernet-phy@1 { reg = <1>; + qca,smarteee-tw-us-1g = <24>; }; }; From f3dbb291814a72b17875d7e261a3bc53f8299692 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Mon, 18 Jan 2021 11:54:18 +0100 Subject: [PATCH 52/71] arm64: dts: imx8mq-librem5: Mark charger IRQ as High-Z MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is consistent with other IRQs and makes keeps currents low. Signed-off-by: Guido Günther Signed-off-by: Martin Kepplinger Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index f85d30a0c2cb..9928e941ee21 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -276,7 +276,7 @@ MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83 pinctrl_charger_in: chargeringrp { fsl,pins = < /* CHRG_INT */ - MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x00 + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 /* CHG_STATUS_B */ MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 >; From 99e71c029213d3cfcc4f39a534c73d1828ffb341 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Mon, 18 Jan 2021 11:54:19 +0100 Subject: [PATCH 53/71] arm64: dts: imx8mq-librem5: Don't mark buck3 as always on MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the pmic driver fixed we can now shut off the regulator in the gpc. Signed-off-by: Guido Günther Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 9928e941ee21..95d710831f28 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -679,7 +679,6 @@ buck3_reg: BUCK3 { regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; rohm,dvs-run-voltage = <900000>; - regulator-always-on; }; buck4_reg: BUCK4 { From d5edcf2cbf5e28008e8f7eed63305bbfd14637cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Mon, 18 Jan 2021 11:54:20 +0100 Subject: [PATCH 54/71] arm64: dts: imx8mq-librem5: Add usb-c chip as supplier for the charger MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The tps65982 feeds the bq25895 charge controller on the Librem 5. Signed-off-by: Guido Günther Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 95d710831f28..d7d807cd72b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -928,6 +928,7 @@ bq25895: charger@6a { ti,use-vinmin-threshold = <1>; /* enable VINDPM */ ti,vinmin-threshold = <3900000>; /* uV */ monitored-battery = <&bat>; + power-supplies = <&typec_pd>; }; }; From 7127e3b5d93d8a1ee01eab04011ab6d1fff79ee1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Mon, 18 Jan 2021 11:54:21 +0100 Subject: [PATCH 55/71] arm64: dts: imx8mq-librem5: Add LCD_1V8 regulator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's a supply for to touch and LCD. Signed-off-by: Guido Günther Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index d7d807cd72b3..f77b51d3c132 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -82,6 +82,20 @@ reg_hub: regulator-hub { enable-active-high; }; + reg_lcd_1v8: regulator-lcd-1v8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsien>; + regulator-name = "LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_vdd_1v8>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* Otherwise i2c3 is not functional */ + regulator-always-on; + }; + reg_lcd_3v4: regulator-lcd-3v4 { compatible = "regulator-fixed"; regulator-name = "LCD_3V4"; @@ -892,6 +906,7 @@ touchscreen@38 { interrupts = <27 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <720>; touchscreen-size-y = <1440>; + vcc-supply = <®_lcd_1v8>; }; }; From 584ea5b1499ee6e07cf82d2d12c1862c38b3d089 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Mon, 18 Jan 2021 11:54:22 +0100 Subject: [PATCH 56/71] arm64: dts: imx8mq-librem5: enable the LCD panel This enables the Librem5's ft8006p based LCD panel driven by the imx8mq's Northwest Logic DSI IP core and mxsfb display controller. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5.dtsi | 53 ++++++++++++++++++- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index f77b51d3c132..bf86402cda30 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -310,6 +310,17 @@ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x83 >; }; + pinctrl_dsirst: dsirstgrp { + fsl,pins = < + /* DSI_RST */ + MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x83 + /* DSI_TE */ + MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x83 + /* TP_RST */ + MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x83 + >; + }; + pinctrl_ecspi1: ecspigrp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x83 @@ -817,12 +828,12 @@ regulator@3e { compatible = "tps65132"; reg = <0x3e>; - outp { + reg_lcd_avdd: outp { regulator-name = "LCD_AVDD"; vin-supply = <®_lcd_3v4>; }; - outn { + reg_lcd_avee: outn { regulator-name = "LCD_AVEE"; vin-supply = <®_lcd_3v4>; }; @@ -947,6 +958,44 @@ bq25895: charger@6a { }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + lcd_panel: panel@0 { + compatible = "mantix,mlaf057we51-x"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsirst>; + avdd-supply = <®_lcd_avdd>; + avee-supply = <®_lcd_avee>; + vddi-supply = <®_lcd_1v8>; + backlight = <&backlight_dsi>; + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + &pgc_gpu { power-supply = <&buck3_reg>; }; From a8bb83c8c7a17e83e04801d0678e93654f9bfaee Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Mon, 18 Jan 2021 11:54:23 +0100 Subject: [PATCH 57/71] arm64: dts: imx8mq-librem5: set regulators boot-on Expect all those regulators to be turned on initially. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index bf86402cda30..06a4799b6aeb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -682,6 +682,7 @@ buck1_reg: BUCK1 { regulator-name = "buck1"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; + regulator-boot-on; regulator-ramp-delay = <1250>; rohm,dvs-run-voltage = <900000>; rohm,dvs-idle-voltage = <850000>; @@ -693,6 +694,7 @@ buck2_reg: BUCK2 { regulator-name = "buck2"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; + regulator-boot-on; regulator-ramp-delay = <1250>; rohm,dvs-run-voltage = <1000000>; rohm,dvs-idle-voltage = <900000>; @@ -703,6 +705,7 @@ buck3_reg: BUCK3 { regulator-name = "buck3"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; + regulator-boot-on; rohm,dvs-run-voltage = <900000>; }; @@ -717,6 +720,7 @@ buck5_reg: BUCK5 { regulator-name = "buck5"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; + regulator-boot-on; regulator-always-on; }; @@ -724,6 +728,7 @@ buck6_reg: BUCK6 { regulator-name = "buck6"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; regulator-always-on; }; @@ -731,6 +736,7 @@ buck7_reg: BUCK7 { regulator-name = "buck7"; regulator-min-microvolt = <1605000>; regulator-max-microvolt = <1995000>; + regulator-boot-on; regulator-always-on; }; @@ -738,6 +744,7 @@ buck8_reg: BUCK8 { regulator-name = "buck8"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; + regulator-boot-on; regulator-always-on; }; @@ -745,6 +752,7 @@ ldo1_reg: LDO1 { regulator-name = "ldo1"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; /* leave on for snvs power button */ regulator-always-on; }; @@ -753,6 +761,7 @@ ldo2_reg: LDO2 { regulator-name = "ldo2"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; + regulator-boot-on; /* leave on for snvs power button */ regulator-always-on; }; @@ -761,6 +770,7 @@ ldo3_reg: LDO3 { regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; regulator-always-on; }; @@ -768,6 +778,7 @@ ldo4_reg: LDO4 { regulator-name = "ldo4"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; + regulator-boot-on; regulator-always-on; }; @@ -784,6 +795,7 @@ ldo6_reg: LDO6 { regulator-name = "ldo6"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; + regulator-boot-on; regulator-always-on; }; @@ -792,6 +804,7 @@ ldo7_reg: LDO7 { regulator-name = "ldo7"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; regulator-always-on; }; }; From f2047594e865bac597ab5056cd7d573be96ecfe1 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Mon, 18 Jan 2021 11:54:25 +0100 Subject: [PATCH 58/71] arm64: dts: Add Librem5 Evergreen Add librem5-r4 with specifics to that revision like the near-level, battery and charger properties. For schematics and more information, see https://developer.puri.sm/Librem5/Hardware_Reference/Evergreen.html Signed-off-by: Martin Kepplinger Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mq-librem5-r4.dts | 35 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 17fc731da700..44a20b89b1ef 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r4.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts new file mode 100644 index 000000000000..cbfb49aa2563 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Purism SPC + +/dts-v1/; + +#include "imx8mq-librem5.dtsi" + +/ { + model = "Purism Librem 5r4"; + compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; +}; + +&accel_gyro { + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; +}; + +&bat { + maxim,rsns-microohm = <1667>; +}; + +&bq25895 { + ti,battery-regulation-voltage = <4200000>; /* uV */ + ti,charge-current = <1500000>; /* uA */ + ti,termination-current = <144000>; /* uA */ +}; + +&led_backlight { + led-max-microamp = <25000>; +}; + +&proximity { + proximity-near-level = <10>; +}; From 189f65864f4eeb430bee0e6a18b7f871bf218878 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 19 Jan 2021 07:42:57 -0600 Subject: [PATCH 59/71] arm64: dts: imx8mn: Add fspi node The i.MX8M Nano has the same Flexspi controller used in the i.MX8M Mini. Add the node and disable it by default. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 8004b7f36c77..d0c6f7aca8bc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -889,6 +889,19 @@ usdhc3: mmc@30b60000 { status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, + <&clk IMX8MN_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; From 738f7d40c155ccf0c5564f3d1dce02bea3b09eb1 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 19 Jan 2021 07:42:58 -0600 Subject: [PATCH 60/71] arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM There is a QSPI chip connected to the FlexSPI bus. Enable it. Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mn-beacon-som.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 2120e6485393..de2cd0e3201c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -7,6 +7,7 @@ / { aliases { rtc0 = &rtc; rtc1 = &snvs_rtc; + spi0 = &flexspi; }; usdhc1_pwrseq: usdhc1_pwrseq { @@ -89,6 +90,22 @@ ethphy0: ethernet-phy@0 { }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -318,6 +335,17 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 From 1ab66ad2d7f32de2e553213f2d7afc1158a59d3e Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Tue, 19 Jan 2021 16:51:05 +0100 Subject: [PATCH 61/71] arm64: dts: fsl-ls1012a-rdb: add i2c devices LS1012A-RDB equipped in some i2c devices: - 3x GPIO Expander: PCAL9555A (NXP) - Gyro: FXAS21002 (NXP) - Accelerometer: FXOS8700 (NXP) - Current & Power Monitor: INA220 (TI) This patch add listed devices to dts. Signed-off-by: Pawel Dembicki Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts index f939d656898b..79f155dedb2d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts @@ -7,6 +7,7 @@ */ /dts-v1/; +#include #include "fsl-ls1012a.dtsi" / { @@ -38,6 +39,50 @@ &esdhc1 { &i2c0 { status = "okay"; + + accelerometer@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + interrupt-parent = <&gpio26>; + interrupts = <13 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; + }; + + gyroscope@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + }; + + gpio@24 { + compatible = "nxp,pcal9555a"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@25 { + compatible = "nxp,pcal9555a"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio26: gpio@26 { + compatible = "nxp,pcal9555a"; + reg = <0x26>; + interrupt-parent = <&gpio0>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + current-sensor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <2000>; + }; }; &qspi { From 42c2c068834eab53621a869bd85dac3a915e059c Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Tue, 19 Jan 2021 16:51:06 +0100 Subject: [PATCH 62/71] arm64: dts: fsl-ls1012a-frdm: add spi-uart device This patch adds spi-uart controller to LS1012A-FRDM board dts. Device is equipped in SC16IS740 from NXP. Signed-off-by: Pawel Dembicki Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts index 67702667ed8a..2517528f684f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts @@ -7,6 +7,7 @@ */ /dts-v1/; +#include #include "fsl-ls1012a.dtsi" / { @@ -57,6 +58,26 @@ simple-audio-card,codec { }; }; +&dspi { + bus-num = <0>; + status = "okay"; + + serial@0 { + compatible = "nxp,sc16is740"; + reg = <0>; + spi-max-frequency = <4000000>; + clocks = <&sc16is7xx_clk>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + sc16is7xx_clk: clock-sc16is7xx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; +}; + &duart0 { status = "okay"; }; From 930a0968c6671d5d5cd7a1da569529ee1698b00a Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 21 Jan 2021 16:27:37 +0530 Subject: [PATCH 63/71] arm64: dts: lx2160a: Add flexcan support LX2160A supports two flexcan controllers. Add the support. Enable support further for LX2160A-RDB/QDS. Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-lx2160a-qds.dts | 8 +++++++ .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++++++++++++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 +++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index 16ae3b00cf48..d858d9c8b583 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -33,6 +33,14 @@ sb_3v3: regulator-sb3v3 { }; }; +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + &crypto { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 6f82759f0ce4..5dbf27493e8b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -89,6 +89,22 @@ aquantia_phy2: ethernet-phy@5 { }; }; +&can0 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&can1 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + &esdhc0 { sd-uhs-sdr104; sd-uhs-sdr50; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 451e4430024c..0551f6f4c313 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -895,6 +895,30 @@ esdhc1: esdhc@2150000 { status = "disabled"; }; + can0: can@2180000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_SYSCLK 0>; + clock-names = "ipg", "per"; + fsl,clk-source = <0>; + status = "disabled"; + }; + + can1: can@2190000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_SYSCLK 0>; + clock-names = "ipg", "per"; + fsl,clk-source = <0>; + status = "disabled"; + }; + uart0: serial@21c0000 { compatible = "arm,sbsa-uart","arm,pl011"; reg = <0x0 0x21c0000 0x0 0x1000>; From c9e5ef8cef813f7a83f0e0060ed4ed3eadde183f Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 21 Jan 2021 16:27:38 +0530 Subject: [PATCH 64/71] arm64: dts: ls1028a: Update flexcan properties LS1028A supports two flexcan controllers similar to LX2160A. There's already a compatible entry defined i.e "fsl,lx2160ar1-flexcan" which can be further reused for LS1028A. Please note, "fsl,ls1028ar1-flexcan" compatible entry doesn't exists and can be safely removed. LS1028A has a single peripheral clock (i.e platform clock) source connected to both "ipg" and "per" and therefore, remove "sysclk" as clock source from device-tree. Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 045739dbcb17..15143627ac8c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -418,21 +418,25 @@ esdhc1: mmc@2150000 { }; can0: can@2180000 { - compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; + compatible = "fsl,lx2160ar1-flexcan"; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = ; - clocks = <&sysclk>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(2)>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg", "per"; status = "disabled"; }; can1: can@2190000 { - compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; + compatible = "fsl,lx2160ar1-flexcan"; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = ; - clocks = <&sysclk>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(2)>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg", "per"; status = "disabled"; }; From 837ae08d95f2fe1ba33aa33b0256648b717e87b1 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 21 Jan 2021 16:27:39 +0530 Subject: [PATCH 65/71] arm64: dts: ls1028a: Enable flexcan support for LS1028A-RDB/QDS LS1028A-RDB/QDS provides support for flexcan. Add the properties. Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 8 ++++++++ .../arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 16 ++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index c0786b713791..fbcba9cb8503 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -109,6 +109,14 @@ qds_phy1: ethernet-phy@5 { }; }; +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + &dspi0 { bus-num = <0>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index c1d1ba459307..41ae6e7675ba 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -85,6 +85,22 @@ simple-audio-card,codec { }; }; +&can0 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&can1 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + &esdhc { sd-uhs-sdr104; sd-uhs-sdr50; From 663a5b5efa510b91fa35a0a08eae9ec6a364ebcb Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 25 Jan 2021 19:47:32 +0100 Subject: [PATCH 66/71] arm64: dts: zii-ultra: add sound support This adds all the necessary nodes to get audio support on both the RMB3 and Zest boards. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mq-zii-ultra-rmb3.dts | 91 +++++++++++++++++ .../dts/freescale/imx8mq-zii-ultra-zest.dts | 30 ++++++ .../boot/dts/freescale/imx8mq-zii-ultra.dtsi | 98 +++++++++++++++++++ 3 files changed, 219 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts index bfad4b885905..b3743f96f899 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts @@ -10,6 +10,56 @@ / { model = "ZII Ultra RMB3 Board"; compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq"; + + sound1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "front"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound1_codec>; + simple-audio-card,frame-master = <&sound1_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack Front"; + simple-audio-card,routing = + "Headphone Jack Front", "HPA1 HPLEFT", + "Headphone Jack Front", "HPA1 HPRIGHT", + "HPA1 LEFTIN", "HPL", + "HPA1 RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa1>; + + sound1_cpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + sound1_codec: simple-audio-card,codec { + sound-dai = <&codec1>; + clocks = <&cs2000>; + }; + }; + + sound2 { + compatible = "simple-audio-card"; + simple-audio-card,name = "periph"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound2_codec>; + simple-audio-card,frame-master = <&sound2_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack Back"; + simple-audio-card,routing = + "Headphone Jack Back", "HPA1 HPLEFT", + "Headphone Jack Back", "HPA1 HPRIGHT", + "HPA1 LEFTIN", "HPL", + "HPA1 RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa2>; + + sound2_cpu: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + sound2_codec: simple-audio-card,codec { + sound-dai = <&codec2>; + clocks = <&cs2000>; + }; + }; }; &ecspi1 { @@ -27,6 +77,27 @@ nor_flash: flash@0 { }; }; +&hpa2 { + sound-name-prefix = "HPA1"; +}; + +&i2c1 { + codec2: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec2>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + }; +}; + &i2c2 { temp-sense@48 { compatible = "national,lm75"; @@ -79,11 +150,23 @@ touchscreen@2a { }; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + status = "okay"; +}; + &usbhub { swap-dx-lanes = <0>; }; &iomuxc { + pinctrl_codec2: dac2grp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x41 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 @@ -92,4 +175,12 @@ MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 >; }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts index 173b9e9b2bbd..f6130167a1c7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts @@ -10,6 +10,36 @@ / { model = "ZII Ultra Zest Board"; compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq"; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "front"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack Front", + "Headphone", "Headphone Jack Back"; + simple-audio-card,routing = + "Headphone Jack Front", "HPA1 HPLEFT", + "Headphone Jack Front", "HPA1 HPRIGHT", + "Headphone Jack Back", "HPA2 HPLEFT", + "Headphone Jack Back", "HPA2 HPRIGHT", + "HPA1 LEFTIN", "HPL", + "HPA1 RIGHTIN", "HPR", + "HPA2 LEFTIN", "HPL", + "HPA2 RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa1>, <&hpa2>; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&codec1>; + clocks = <&cs2000>; + }; + }; }; &i2c4 { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index fa7a041ffcfd..e6469e15bcbd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -77,6 +77,15 @@ reg_gen_3p3: regulator-gen-3p3 { regulator-always-on; }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + vin-supply = <®_3p3_main>; + regulator-name = "GEN_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-vsd-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2>; @@ -102,6 +111,18 @@ reg_arm: regulator-arm { 900000 0x0>; regulator-always-on; }; + + cs2000_ref: cs2000-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + cs2000_in_dummy: cs2000-in-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; }; &A53_0 { @@ -286,6 +307,16 @@ ucs1002: charger@32 { <18 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "a_det", "alert"; }; + + hpa2: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa2>; + reg = <0x60>; + power-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0_main>; + sound-name-prefix = "HPA2"; + }; }; &i2c2 { @@ -378,11 +409,36 @@ vgen6_reg: vgen6 { }; }; + codec1: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec1>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + }; + eeprom@54 { compatible = "atmel,24c128"; reg = <0x54>; }; + hpa1: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa1>; + reg = <0x60>; + power-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0_main>; + sound-name-prefix = "HPA1"; + }; + ds1341: rtc@68 { compatible = "dallas,ds1341"; reg = <0x68>; @@ -407,6 +463,16 @@ watchdog@38 { compatible = "zii,rave-wdt"; reg = <0x38>; }; + + cs2000: clkgen@4e { + compatible = "cirrus,cs2000-cp"; + reg = <0x4e>; + #clock-cells = <0>; + clock-names = "clk_in", "ref_clk"; + clocks = <&cs2000_in_dummy>, <&cs2000_ref>; + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24000000>; + }; }; &i2c4 { @@ -416,6 +482,12 @@ &i2c4 { status = "okay"; }; +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -551,6 +623,12 @@ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 >; }; + pinctrl_codec1: dac1grp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x41 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -642,12 +720,32 @@ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + >; + }; + pinctrl_switch_irq: switchgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 >; }; + pinctrl_tpa1: tpa6130-1grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x41 + >; + }; + + pinctrl_tpa2: tpa6130-2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 + >; + }; + pinctrl_ts: tsgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96 From 71a8434857d51c1aa15b17338626b273f5e58be1 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 25 Jan 2021 19:47:33 +0100 Subject: [PATCH 67/71] arm64: dts: zii-ultra: fix i2c pin configuration Reduce slew rate and set drive strength to 105 Ohm. The previous settings had some issues with signal ringing, due to the slew rate being too fast. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-zii-ultra.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index e6469e15bcbd..aa05d5fd1b3b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -661,29 +661,29 @@ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6 pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022 + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000a2 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000022 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000a2 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022 + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000a2 >; }; pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022 + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000a2 >; }; From f2615e598a50f8077e6ec70e2060ca0b5d8f989f Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 25 Jan 2021 19:47:34 +0100 Subject: [PATCH 68/71] arm64: dts: zii-ultra: limit USB ports to USB2 speed The internal USB is connected to a USB2 hub, the front-panel USB is wired directly, but does not support USB3 speeds electrically. Limit both ports accordingly. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index aa05d5fd1b3b..edbde9ed4caf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -540,6 +540,7 @@ &usb3_phy0 { &usb_dwc3_0 { dr_mode = "host"; + maximum-speed = "high-speed"; status = "okay"; }; @@ -550,6 +551,7 @@ &usb3_phy1 { &usb_dwc3_1 { dr_mode = "host"; + maximum-speed = "high-speed"; status = "okay"; }; From b53e7e0c65bfb68aee4fba83eb3b6ec74f0869ae Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 25 Jan 2021 19:47:35 +0100 Subject: [PATCH 69/71] arm64: dts: zii-ultra: only trigger IRQ on falling edge ucs1002 ALERT pin The ALERT signaling happens on the falling edge of the signal, as rising edge doesn't really have any notion, as it may happen much later (due to shared IRQ line) or too early if the chip resolves the fault itself. So only trigger the IRQ on the edge we are actually interested in. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index edbde9ed4caf..4dc8383478ee 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -304,7 +304,7 @@ ucs1002: charger@32 { reg = <0x32>; interrupt-parent = <&gpio3>; interrupts = <17 IRQ_TYPE_EDGE_BOTH>, - <18 IRQ_TYPE_EDGE_BOTH>; + <18 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "a_det", "alert"; }; From 370d82d3facfb3709c3f4c793229f5b8f5c7001e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 25 Jan 2021 19:47:36 +0100 Subject: [PATCH 70/71] arm64: dts: zii-rmb3: enable RMI4 reduced reporting To use the reduced reporting mode the threshold values need to be set explicitly. Configure the threshold to be less than 0.5% of the full touchscreen range. This seems to be a good compromise between system load and input accurancy. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts index b3743f96f899..631e01c1b9fd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts @@ -127,6 +127,8 @@ rmi4-f11@11 { touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; + syna,delta-x-threshold = <5>; + syna,delta-y-threshold = <10>; }; rmi4-f12@12 { From da1a6b8bec881b67f0e234ed19e8b7e2fb1e7812 Mon Sep 17 00:00:00 2001 From: Adrien Grassein Date: Thu, 28 Jan 2021 20:35:53 +0100 Subject: [PATCH 71/71] arm64: dts: imx: Add i.mx8mm nitrogen basic dts support Tested with a basic Build Root configuration booting from sdcard. Signed-off-by: Adrien Grassein Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mm-nitrogen-r2.dts | 393 ++++++++++++++++++ 2 files changed, 394 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 44a20b89b1ef..6438db3822f8 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts new file mode 100644 index 000000000000..c0c384d76147 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Boundary Devices i.MX8MMini Nitrogen8MM Rev2 board. + * Adrien Grassein + */ +/dts-v1/; +#include "imx8mm.dtsi" + +/ { + model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2"; + compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm"; +}; + +&A53_0 { + cpu-supply = <®_buck3>; +}; + +&A53_1 { + cpu-supply = <®_buck3>; +}; + +&A53_2 { + cpu-supply = <®_buck3>; +}; + +&A53_3 { + cpu-supply = <®_buck3>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts-extended = <&gpio3 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "nxp,pf8121a"; + reg = <0x8>; + + regulators { + reg_ldo1: ldo1 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo2: ldo2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo3: ldo3 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo4: ldo4 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck1: buck1 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck2: buck2 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck3: buck3 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck4: buck4 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck5: buck5 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck6: buck6 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck7: buck7 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vsnvs: vsnvs { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + i2cmux@70 { + compatible = "nxp,pca9540"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c3 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3a_rv4162>; + interrupts-extended = <&gpio4 22 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; + }; + }; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + bus-width = <8>; + sdhci-caps-mask = <0x80000000 0x0>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* sdcard */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vqmmc-supply = <®_ldo2>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x159 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x09 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3a_rv4162: i2c3a-rv4162grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x141 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 + >; + }; +};