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Merge branch 'icc-sm6350' into icc-next
Update dt-bindings, driver and dts in order to configure the QoS registers for the various SM6350 interconnects. * icc-sm6350 dt-bindings: interconnect: qcom,sm6350-rpmh: Add clocks for QoS interconnect: qcom: icc-rpmh: Get parent's regmap for nested NoCs interconnect: qcom: sm6350: Remove empty BCM arrays interconnect: qcom: sm6350: enable QoS configuration Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-0-6af348cb9c69@fairphone.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov
commit
60b52af082
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@ -12,9 +12,6 @@ maintainers:
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description:
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Qualcomm RPMh-based interconnect provider on SM6350.
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allOf:
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- $ref: qcom,rpmh-common.yaml#
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properties:
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compatible:
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enum:
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@ -30,7 +27,9 @@ properties:
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reg:
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maxItems: 1
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'#interconnect-cells': true
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clocks:
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minItems: 1
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maxItems: 2
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patternProperties:
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'^interconnect-[a-z0-9\-]+$':
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@ -46,8 +45,6 @@ patternProperties:
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- qcom,sm6350-clk-virt
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- qcom,sm6350-compute-noc
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'#interconnect-cells': true
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required:
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- compatible
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@ -57,10 +54,54 @@ required:
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- compatible
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- reg
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allOf:
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- $ref: qcom,rpmh-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm6350-aggre1-noc
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then:
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properties:
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clocks:
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items:
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- description: aggre UFS PHY AXI clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm6350-aggre2-noc
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then:
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properties:
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clocks:
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items:
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- description: aggre USB3 PRIM AXI clock
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- description: RPMH CC IPA clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm6350-aggre1-noc
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- qcom,sm6350-aggre2-noc
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then:
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required:
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- clocks
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else:
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properties:
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clocks: false
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm6350.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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config_noc: interconnect@1500000 {
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compatible = "qcom,sm6350-config-noc";
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reg = <0x01500000 0x28000>;
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@ -68,14 +109,16 @@ examples:
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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system_noc: interconnect@1620000 {
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compatible = "qcom,sm6350-system-noc";
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reg = <0x01620000 0x17080>;
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aggre2_noc: interconnect@1700000 {
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compatible = "qcom,sm6350-aggre2-noc";
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reg = <0x01700000 0x1f880>;
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&rpmhcc RPMH_IPA_CLK>;
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clk_virt: interconnect-clk-virt {
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compatible = "qcom,sm6350-clk-virt";
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compute_noc: interconnect-compute-noc {
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compatible = "qcom,sm6350-compute-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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@ -308,14 +308,19 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
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struct resource *res;
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void __iomem *base;
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(base))
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goto skip_qos_config;
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/* Try parent's regmap first */
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qp->regmap = dev_get_regmap(dev->parent, NULL);
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if (!qp->regmap) {
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(base))
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goto skip_qos_config;
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qp->regmap = devm_regmap_init_mmio(dev, base, desc->config);
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if (IS_ERR(qp->regmap)) {
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dev_info(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap));
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goto skip_qos_config;
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qp->regmap = devm_regmap_init_mmio(dev, base, desc->config);
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if (IS_ERR(qp->regmap)) {
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dev_info(dev, "Skipping QoS, regmap failed; %ld\n",
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PTR_ERR(qp->regmap));
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goto skip_qos_config;
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}
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}
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qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks);
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|
|
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@ -150,26 +150,50 @@ static struct qcom_icc_node qhm_a1noc_cfg = {
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.link_nodes = { &srvc_aggre1_noc },
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};
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static struct qcom_icc_qosbox qhm_qup_0_qos = {
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.num_ports = 1,
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.port_offsets = { 0xa000 },
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.prio = 2,
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.urg_fwd = 0,
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};
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static struct qcom_icc_node qhm_qup_0 = {
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.name = "qhm_qup_0",
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.channels = 1,
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.buswidth = 4,
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.qosbox = &qhm_qup_0_qos,
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.num_links = 1,
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_qosbox xm_emmc_qos = {
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.num_ports = 1,
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.port_offsets = { 0x7000 },
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.prio = 2,
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.urg_fwd = 0,
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};
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static struct qcom_icc_node xm_emmc = {
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.name = "xm_emmc",
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.channels = 1,
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.buswidth = 8,
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.qosbox = &xm_emmc_qos,
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.num_links = 1,
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_qosbox xm_ufs_mem_qos = {
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.num_ports = 1,
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.port_offsets = { 0x8000 },
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.prio = 4,
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.urg_fwd = 0,
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};
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static struct qcom_icc_node xm_ufs_mem = {
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.name = "xm_ufs_mem",
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.channels = 1,
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.buswidth = 8,
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.qosbox = &xm_ufs_mem_qos,
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.num_links = 1,
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.link_nodes = { &qns_a1noc_snoc },
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};
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@ -182,58 +206,113 @@ static struct qcom_icc_node qhm_a2noc_cfg = {
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.link_nodes = { &srvc_aggre2_noc },
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};
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static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
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.num_ports = 1,
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.port_offsets = { 0xb000 },
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.prio = 2,
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.urg_fwd = 0,
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};
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static struct qcom_icc_node qhm_qdss_bam = {
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.name = "qhm_qdss_bam",
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.channels = 1,
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.buswidth = 4,
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.qosbox = &qhm_qdss_bam_qos,
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.num_links = 1,
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_qosbox qhm_qup_1_qos = {
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.num_ports = 1,
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.port_offsets = { 0x9000 },
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.prio = 2,
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.urg_fwd = 0,
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};
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static struct qcom_icc_node qhm_qup_1 = {
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.name = "qhm_qup_1",
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.channels = 1,
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.buswidth = 4,
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.qosbox = &qhm_qup_1_qos,
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.num_links = 1,
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_qosbox qxm_crypto_qos = {
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.num_ports = 1,
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.port_offsets = { 0x6000 },
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.prio = 2,
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.urg_fwd = 0,
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};
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static struct qcom_icc_node qxm_crypto = {
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.name = "qxm_crypto",
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.channels = 1,
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.buswidth = 8,
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.qosbox = &qxm_crypto_qos,
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.num_links = 1,
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_qosbox qxm_ipa_qos = {
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.num_ports = 1,
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.port_offsets = { 0x7000 },
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.prio = 2,
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.urg_fwd = 0,
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};
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static struct qcom_icc_node qxm_ipa = {
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.name = "qxm_ipa",
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.channels = 1,
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.buswidth = 8,
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.qosbox = &qxm_ipa_qos,
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.num_links = 1,
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_qosbox xm_qdss_etr_qos = {
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.num_ports = 1,
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.port_offsets = { 0xc000 },
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.prio = 2,
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.urg_fwd = 0,
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};
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static struct qcom_icc_node xm_qdss_etr = {
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.name = "xm_qdss_etr",
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.channels = 1,
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.buswidth = 8,
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.qosbox = &xm_qdss_etr_qos,
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.num_links = 1,
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_qosbox xm_sdc2_qos = {
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.num_ports = 1,
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.port_offsets = { 0x18000 },
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.prio = 2,
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.urg_fwd = 0,
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};
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static struct qcom_icc_node xm_sdc2 = {
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.name = "xm_sdc2",
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.channels = 1,
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.buswidth = 8,
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.qosbox = &xm_sdc2_qos,
|
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.num_links = 1,
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.link_nodes = { &qns_a2noc_snoc },
|
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};
|
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|
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static struct qcom_icc_qosbox xm_usb3_0_qos = {
|
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.num_ports = 1,
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.port_offsets = { 0xd000 },
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.prio = 2,
|
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.urg_fwd = 0,
|
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};
|
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|
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static struct qcom_icc_node xm_usb3_0 = {
|
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.name = "xm_usb3_0",
|
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.channels = 1,
|
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.buswidth = 8,
|
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.qosbox = &xm_usb3_0_qos,
|
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.num_links = 1,
|
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.link_nodes = { &qns_a2noc_snoc },
|
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};
|
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|
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@ -278,18 +357,34 @@ static struct qcom_icc_node qup1_core_master = {
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.link_nodes = { &qup1_core_slave },
|
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};
|
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|
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static struct qcom_icc_qosbox qnm_npu_qos = {
|
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.num_ports = 2,
|
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.port_offsets = { 0xf000, 0x11000 },
|
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.prio = 0,
|
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.urg_fwd = 1,
|
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};
|
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|
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static struct qcom_icc_node qnm_npu = {
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.name = "qnm_npu",
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.channels = 2,
|
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.buswidth = 32,
|
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.qosbox = &qnm_npu_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_cdsp_gemnoc },
|
||||
};
|
||||
|
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static struct qcom_icc_qosbox qxm_npu_dsp_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x13000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qxm_npu_dsp = {
|
||||
.name = "qxm_npu_dsp",
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &qxm_npu_dsp_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_cdsp_gemnoc },
|
||||
};
|
||||
|
|
@ -401,19 +496,35 @@ static struct qcom_icc_node qhm_cnoc_dc_noc = {
|
|||
&qhs_gemnoc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox acm_apps_qos = {
|
||||
.num_ports = 2,
|
||||
.port_offsets = { 0x2f100, 0x2f000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node acm_apps = {
|
||||
.name = "acm_apps",
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.qosbox = &acm_apps_qos,
|
||||
.num_links = 2,
|
||||
.link_nodes = { &qns_llcc,
|
||||
&qns_gem_noc_snoc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox acm_sys_tcu_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x35000 },
|
||||
.prio = 6,
|
||||
.urg_fwd = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node acm_sys_tcu = {
|
||||
.name = "acm_sys_tcu",
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &acm_sys_tcu_qos,
|
||||
.num_links = 2,
|
||||
.link_nodes = { &qns_llcc,
|
||||
&qns_gem_noc_snoc },
|
||||
|
|
@ -429,53 +540,101 @@ static struct qcom_icc_node qhm_gemnoc_cfg = {
|
|||
&qhs_mdsp_ms_mpu_cfg },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qnm_cmpnoc_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x2e000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_cmpnoc = {
|
||||
.name = "qnm_cmpnoc",
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &qnm_cmpnoc_qos,
|
||||
.num_links = 2,
|
||||
.link_nodes = { &qns_llcc,
|
||||
&qns_gem_noc_snoc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x30000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mnoc_hf = {
|
||||
.name = "qnm_mnoc_hf",
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &qnm_mnoc_hf_qos,
|
||||
.num_links = 2,
|
||||
.link_nodes = { &qns_llcc,
|
||||
&qns_gem_noc_snoc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x34000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mnoc_sf = {
|
||||
.name = "qnm_mnoc_sf",
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &qnm_mnoc_sf_qos,
|
||||
.num_links = 2,
|
||||
.link_nodes = { &qns_llcc,
|
||||
&qns_gem_noc_snoc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qnm_snoc_gc_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x32000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_snoc_gc = {
|
||||
.name = "qnm_snoc_gc",
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &qnm_snoc_gc_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_llcc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x31000 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_snoc_sf = {
|
||||
.name = "qnm_snoc_sf",
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.qosbox = &qnm_snoc_sf_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_llcc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qxm_gpu_qos = {
|
||||
.num_ports = 2,
|
||||
.port_offsets = { 0x33000, 0x33080 },
|
||||
.prio = 0,
|
||||
.urg_fwd = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qxm_gpu = {
|
||||
.name = "qxm_gpu",
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.qosbox = &qxm_gpu_qos,
|
||||
.num_links = 2,
|
||||
.link_nodes = { &qns_llcc,
|
||||
&qns_gem_noc_snoc },
|
||||
|
|
@ -497,50 +656,98 @@ static struct qcom_icc_node qhm_mnoc_cfg = {
|
|||
.link_nodes = { &srvc_mnoc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qnm_video0_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xf000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_video0 = {
|
||||
.name = "qnm_video0",
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &qnm_video0_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_mem_noc_sf },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qnm_video_cvp_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xe000 },
|
||||
.prio = 5,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_video_cvp = {
|
||||
.name = "qnm_video_cvp",
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &qnm_video_cvp_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_mem_noc_sf },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qxm_camnoc_hf_qos = {
|
||||
.num_ports = 2,
|
||||
.port_offsets = { 0xa000, 0xb000 },
|
||||
.prio = 3,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qxm_camnoc_hf = {
|
||||
.name = "qxm_camnoc_hf",
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.qosbox = &qxm_camnoc_hf_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_mem_noc_hf },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qxm_camnoc_icp_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xd000 },
|
||||
.prio = 5,
|
||||
.urg_fwd = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qxm_camnoc_icp = {
|
||||
.name = "qxm_camnoc_icp",
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &qxm_camnoc_icp_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_mem_noc_sf },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qxm_camnoc_sf_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0x9000 },
|
||||
.prio = 3,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qxm_camnoc_sf = {
|
||||
.name = "qxm_camnoc_sf",
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &qxm_camnoc_sf_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_mem_noc_sf },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qxm_mdp0_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xc000 },
|
||||
.prio = 3,
|
||||
.urg_fwd = 1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qxm_mdp0 = {
|
||||
.name = "qxm_mdp0",
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.qosbox = &qxm_mdp0_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_mem_noc_hf },
|
||||
};
|
||||
|
|
@ -616,19 +823,35 @@ static struct qcom_icc_node qnm_gemnoc = {
|
|||
&xs_qdss_stm },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox qxm_pimem_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xd000 },
|
||||
.prio = 2,
|
||||
.urg_fwd = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qxm_pimem = {
|
||||
.name = "qxm_pimem",
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &qxm_pimem_qos,
|
||||
.num_links = 2,
|
||||
.link_nodes = { &qns_gemnoc_gc,
|
||||
&qxs_imem },
|
||||
};
|
||||
|
||||
static struct qcom_icc_qosbox xm_gic_qos = {
|
||||
.num_ports = 1,
|
||||
.port_offsets = { 0xb000 },
|
||||
.prio = 3,
|
||||
.urg_fwd = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node xm_gic = {
|
||||
.name = "xm_gic",
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.qosbox = &xm_gic_qos,
|
||||
.num_links = 1,
|
||||
.link_nodes = { &qns_gemnoc_gc },
|
||||
};
|
||||
|
|
@ -1388,11 +1611,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
|
|||
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sm6350_aggre1_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x15080,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm6350_aggre1_noc = {
|
||||
.config = &sm6350_aggre1_noc_regmap_config,
|
||||
.nodes = aggre1_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
|
||||
.bcms = aggre1_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
|
||||
.qos_requires_clocks = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
|
||||
|
|
@ -1413,11 +1646,21 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
|
|||
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sm6350_aggre2_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x1f880,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm6350_aggre2_noc = {
|
||||
.config = &sm6350_aggre2_noc_regmap_config,
|
||||
.nodes = aggre2_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
|
||||
.bcms = aggre2_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
|
||||
.qos_requires_clocks = true,
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
|
||||
|
|
@ -1459,7 +1702,16 @@ static struct qcom_icc_node * const compute_noc_nodes[] = {
|
|||
[SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sm6350_compute_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x1f880,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm6350_compute_noc = {
|
||||
.config = &sm6350_compute_noc_regmap_config,
|
||||
.nodes = compute_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
|
||||
.bcms = compute_noc_bcms,
|
||||
|
|
@ -1526,20 +1778,24 @@ static const struct qcom_icc_desc sm6350_config_noc = {
|
|||
.num_bcms = ARRAY_SIZE(config_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const dc_noc_nodes[] = {
|
||||
[MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
|
||||
[SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
|
||||
[SLAVE_LLCC_CFG] = &qhs_llcc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sm6350_dc_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x3200,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm6350_dc_noc = {
|
||||
.config = &sm6350_dc_noc_regmap_config,
|
||||
.nodes = dc_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
|
||||
.bcms = dc_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
|
||||
|
|
@ -1566,7 +1822,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
|
|||
[SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sm6350_gem_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x3e200,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm6350_gem_noc = {
|
||||
.config = &sm6350_gem_noc_regmap_config,
|
||||
.nodes = gem_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
|
||||
.bcms = gem_noc_bcms,
|
||||
|
|
@ -1593,16 +1858,22 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
|
|||
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config sm6350_mmss_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x1c100,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm6350_mmss_noc = {
|
||||
.config = &sm6350_mmss_noc_regmap_config,
|
||||
.nodes = mmss_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
|
||||
.bcms = mmss_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const npu_noc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const npu_noc_nodes[] = {
|
||||
[MASTER_NPU_SYS] = &amm_npu_sys,
|
||||
[MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
|
||||
|
|
@ -1620,8 +1891,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = {
|
|||
static const struct qcom_icc_desc sm6350_npu_noc = {
|
||||
.nodes = npu_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(npu_noc_nodes),
|
||||
.bcms = npu_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(npu_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const system_noc_bcms[] = {
|
||||
|
|
@ -1653,7 +1922,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
|
|||
[SLAVE_TCU] = &xs_sys_tcu_cfg,
|
||||
};
|
||||
|
||||
static const struct regmap_config sm6350_system_noc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x17080,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm6350_system_noc = {
|
||||
.config = &sm6350_system_noc_regmap_config,
|
||||
.nodes = system_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(system_noc_nodes),
|
||||
.bcms = system_noc_bcms,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user