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drm/i915/display: convert intel_display.c to struct intel_display

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Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_display.c to struct
intel_display.

This exposes a couple of outside issues that need to be fixed as well,
in a register macro and a DSI PLL stub.

Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1c0bafcb978d1cf4f4d54be2f497386f5302f7c8.1741084010.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2025-03-04 12:27:34 +02:00
parent 055e8af4c9
commit 6069b21f58
3 changed files with 413 additions and 431 deletions
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834
drivers/gpu/drm/i915/display/intel_display.c
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File diff suppressed because it is too large Load Diff

6
drivers/gpu/drm/i915/display/vlv_dsi_pll.h
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@ -23,7 +23,6 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
struct intel_crtc_state *config);
void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
int bxt_dsi_pll_compute(struct intel_encoder *encoder,
struct intel_crtc_state *config);
void bxt_dsi_pll_enable(struct intel_encoder *encoder,
@ -34,9 +33,14 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
#ifdef I915
bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
void assert_dsi_pll_enabled(struct intel_display *display);
void assert_dsi_pll_disabled(struct intel_display *display);
#else
static inline bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
{
return false;
}
static inline void assert_dsi_pll_enabled(struct intel_display *display)
{
}

4
drivers/gpu/drm/i915/i915_reg.h
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@ -4165,8 +4165,8 @@ enum skl_power_gate {
_MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
#define _VLV_PIPE_MSA_MISC_A 0x70048
#define VLV_PIPE_MSA_MISC(pipe) \
_MMIO_PIPE2(dev_priv, pipe, _VLV_PIPE_MSA_MISC_A)
#define VLV_PIPE_MSA_MISC(__display, pipe) \
_MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A)
#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */