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Merge branch 'pci/aspm'
- Avoid L0s for Realtek RTS525A, where it causes an AER interrupt storm (Max Lee) - Program the same ASPM Control values for every function of multi-function devices, as recommended by the PCIe spec (Krishna Chaitanya Chundru) - Avoid ASPM L0s, L1, and L1 PM Substates based on 'aspm-no-l0s', 'aspm-no-l1' [1], and 'aspm-no-l1ss' DT properties (Krishna Chaitanya Chundru) * pci/aspm: PCI/ASPM: Mask ASPM states based on Devicetree properties PCI/ASPM: Disable/restore ASPM on every function for multi-function devices PCI/ASPM: Use pcie_capability_clear_and_set_word() for ASPM disable/restore PCI/ASPM: Avoid L0s for Realtek RTS525A
This commit is contained in:
Bjorn Helgaas
commit
606866edbc
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@ -839,116 +839,6 @@ static void aspm_l1ss_init(struct pcie_link_state *link)
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#define FLAG(x, y, d) (((x) & (PCIE_LINK_STATE_##y)) ? d : "")
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static void pcie_aspm_override_default_link_state(struct pcie_link_state *link)
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{
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struct pci_dev *pdev = link->downstream;
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u32 override;
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/* For devicetree platforms, enable L0s and L1 by default */
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if (of_have_populated_dt()) {
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if (link->aspm_support & PCIE_LINK_STATE_L0S)
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link->aspm_default |= PCIE_LINK_STATE_L0S;
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if (link->aspm_support & PCIE_LINK_STATE_L1)
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link->aspm_default |= PCIE_LINK_STATE_L1;
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override = link->aspm_default & ~link->aspm_enabled;
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if (override)
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pci_info(pdev, "ASPM: default states%s%s\n",
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FLAG(override, L0S, " L0s"),
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FLAG(override, L1, " L1"));
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}
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}
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static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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struct pci_dev *child = link->downstream, *parent = link->pdev;
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u16 parent_lnkctl, child_lnkctl;
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struct pci_bus *linkbus = parent->subordinate;
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if (blacklist) {
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/* Set enabled/disable so that we will disable ASPM later */
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link->aspm_enabled = PCIE_LINK_STATE_ASPM_ALL;
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link->aspm_disable = PCIE_LINK_STATE_ASPM_ALL;
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return;
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}
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/*
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* If ASPM not supported, don't mess with the clocks and link,
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* bail out now.
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*/
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if (!(parent->aspm_l0s_support && child->aspm_l0s_support) &&
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!(parent->aspm_l1_support && child->aspm_l1_support))
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return;
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/* Configure common clock before checking latencies */
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pcie_aspm_configure_common_clock(link);
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/*
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* Re-read upstream/downstream components' register state after
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* clock configuration. L0s & L1 exit latencies in the otherwise
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* read-only Link Capabilities may change depending on common clock
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* configuration (PCIe r5.0, sec 7.5.3.6).
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*/
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pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
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pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
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/* Disable L0s/L1 before updating L1SS config */
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if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
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FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
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pcie_capability_write_word(child, PCI_EXP_LNKCTL,
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child_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL,
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parent_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
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}
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/*
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* Setup L0s state
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*
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* Note that we must not enable L0s in either direction on a
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* given link unless components on both sides of the link each
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* support L0s.
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*/
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if (parent->aspm_l0s_support && child->aspm_l0s_support)
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link->aspm_support |= PCIE_LINK_STATE_L0S;
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if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
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link->aspm_enabled |= PCIE_LINK_STATE_L0S_UP;
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if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
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link->aspm_enabled |= PCIE_LINK_STATE_L0S_DW;
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/* Setup L1 state */
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if (parent->aspm_l1_support && child->aspm_l1_support)
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link->aspm_support |= PCIE_LINK_STATE_L1;
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if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
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link->aspm_enabled |= PCIE_LINK_STATE_L1;
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aspm_l1ss_init(link);
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/* Restore L0s/L1 if they were enabled */
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if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
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FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_lnkctl);
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pcie_capability_write_word(child, PCI_EXP_LNKCTL, child_lnkctl);
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}
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/* Save default state */
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link->aspm_default = link->aspm_enabled;
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pcie_aspm_override_default_link_state(link);
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/* Setup initial capable state. Will be updated later */
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link->aspm_capable = link->aspm_support;
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/* Get and check endpoint acceptable latencies */
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
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pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
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continue;
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pcie_aspm_check_latency(child);
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}
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}
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/* Configure the ASPM L1 substates. Caller must disable L1 first. */
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static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
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{
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@ -985,6 +875,171 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
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PCI_L1SS_CTL1_L1SS_MASK, val);
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}
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static bool pcie_link_has_aspm_override(const struct pcie_link_state *link,
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const char *aspm)
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{
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return (device_property_present(&link->pdev->dev, aspm) ||
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device_property_present(&link->downstream->dev, aspm));
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}
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static void pcie_aspm_override_default_link_state(struct pcie_link_state *link)
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{
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struct pci_dev *pdev = link->downstream;
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u32 override;
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/* For devicetree platforms, enable L0s and L1 by default */
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if (of_have_populated_dt()) {
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bool no_l0s = pcie_link_has_aspm_override(link, "aspm-no-l0s");
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bool no_l1 = pcie_link_has_aspm_override(link, "aspm-no-l1");
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bool no_l1ss = pcie_link_has_aspm_override(link, "aspm-no-l1ss");
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if (no_l0s) {
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link->aspm_support &= ~PCIE_LINK_STATE_L0S;
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link->aspm_default &= ~PCIE_LINK_STATE_L0S;
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link->aspm_enabled &= ~PCIE_LINK_STATE_L0S;
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}
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/*
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* Clear L1SS in hardware before updating aspm_support. Once
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* aspm_capable is derived from aspm_support, pcie_config_aspm_link()
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* skips pcie_config_aspm_l1ss() entirely via the aspm_capable guard,
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* leaving firmware-enabled L1SS substates active in hardware.
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* This applies equally when disabling L1 (which implies L1SS).
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*/
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if ((no_l1 || no_l1ss) && (link->aspm_enabled & PCIE_LINK_STATE_L1SS))
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pcie_config_aspm_l1ss(link, 0);
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if (no_l1) {
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link->aspm_support &= ~(PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_L1SS);
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link->aspm_default &= ~(PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_L1SS);
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link->aspm_enabled &= ~(PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_L1SS);
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} else if (no_l1ss) {
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link->aspm_support &= ~PCIE_LINK_STATE_L1SS;
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link->aspm_default &= ~PCIE_LINK_STATE_L1SS;
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link->aspm_enabled &= ~PCIE_LINK_STATE_L1SS;
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}
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if (link->aspm_support & PCIE_LINK_STATE_L0S)
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link->aspm_default |= PCIE_LINK_STATE_L0S;
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if (link->aspm_support & PCIE_LINK_STATE_L1)
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link->aspm_default |= PCIE_LINK_STATE_L1;
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override = link->aspm_default & ~link->aspm_enabled;
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if (override)
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pci_info(pdev, "ASPM: default states%s%s\n",
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FLAG(override, L0S, " L0s"),
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FLAG(override, L1, " L1"));
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}
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}
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static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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struct pci_dev *child = link->downstream, *parent = link->pdev;
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struct pci_dev *fn;
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u16 parent_lnkctl, child_lnkctl;
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struct pci_bus *linkbus = parent->subordinate;
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if (blacklist) {
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/* Set enabled/disable so that we will disable ASPM later */
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link->aspm_enabled = PCIE_LINK_STATE_ASPM_ALL;
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link->aspm_disable = PCIE_LINK_STATE_ASPM_ALL;
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return;
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}
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/*
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* If ASPM not supported, don't mess with the clocks and link,
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* bail out now.
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*/
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if (!(parent->aspm_l0s_support && child->aspm_l0s_support) &&
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!(parent->aspm_l1_support && child->aspm_l1_support))
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return;
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/* Configure common clock before checking latencies */
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pcie_aspm_configure_common_clock(link);
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/*
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* Re-read upstream/downstream components' register state after
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* clock configuration. L0s & L1 exit latencies in the otherwise
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* read-only Link Capabilities may change depending on common clock
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* configuration (PCIe r5.0, sec 7.5.3.6).
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*/
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pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
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pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
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/* Disable L0s/L1 before updating L1SS config */
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if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
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FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
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list_for_each_entry(fn, &linkbus->devices, bus_list)
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pcie_capability_clear_and_set_word(fn, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC, 0);
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pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC, 0);
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}
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/*
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* Setup L0s state
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*
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* Note that we must not enable L0s in either direction on a
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* given link unless components on both sides of the link each
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* support L0s.
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*/
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if (parent->aspm_l0s_support && child->aspm_l0s_support)
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link->aspm_support |= PCIE_LINK_STATE_L0S;
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if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
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link->aspm_enabled |= PCIE_LINK_STATE_L0S_UP;
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if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
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link->aspm_enabled |= PCIE_LINK_STATE_L0S_DW;
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/* Setup L1 state */
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if (parent->aspm_l1_support && child->aspm_l1_support)
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link->aspm_support |= PCIE_LINK_STATE_L1;
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if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
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link->aspm_enabled |= PCIE_LINK_STATE_L1;
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aspm_l1ss_init(link);
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/* Save default state */
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link->aspm_default = link->aspm_enabled;
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pcie_aspm_override_default_link_state(link);
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/*
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* Restore L0s/L1 if they were enabled, but don't restore any
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* state a Devicetree override just disabled in aspm_support above.
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*/
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if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
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FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
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if (!(link->aspm_support & PCIE_LINK_STATE_L0S)) {
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child_lnkctl &= ~PCI_EXP_LNKCTL_ASPM_L0S;
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parent_lnkctl &= ~PCI_EXP_LNKCTL_ASPM_L0S;
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}
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if (!(link->aspm_support & PCIE_LINK_STATE_L1)) {
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child_lnkctl &= ~PCI_EXP_LNKCTL_ASPM_L1;
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parent_lnkctl &= ~PCI_EXP_LNKCTL_ASPM_L1;
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}
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pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC,
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parent_lnkctl & PCI_EXP_LNKCTL_ASPMC);
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list_for_each_entry(fn, &linkbus->devices, bus_list)
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pcie_capability_clear_and_set_word(fn, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_ASPMC,
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child_lnkctl & PCI_EXP_LNKCTL_ASPMC);
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}
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/* Setup initial capable state. Will be updated later */
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link->aspm_capable = link->aspm_support;
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/* Get and check endpoint acceptable latencies */
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
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pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
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continue;
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pcie_aspm_check_latency(child);
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}
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}
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static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
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{
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pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
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@ -2507,6 +2507,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
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/* Realtek RTS525A generates a Replay Timer Timeout storm when L0s is enabled. */
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x525a, quirk_disable_aspm_l0s);
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static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
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{
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pcie_aspm_remove_cap(dev,
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