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drm/amdgpu: Add SDMA v4.4.2 golden settings

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Add programming of SDMA golden settings for v4.4.2

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2022-10-31 10:46:05 +05:30 committed by Alex Deucher
parent 57a83b2daf
commit 5f09237b82
1 changed files with 16 additions and 5 deletions
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21
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
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@ -96,11 +96,22 @@ static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)
static void sdma_v4_4_2_init_golden_registers(struct amdgpu_device *adev)
{
switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 4, 2):
break;
default:
break;
u32 val;
int i;
for (i = 0; i < adev->sdma.num_instances; i++) {
val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
PIPE_INTERLEAVE_SIZE, 0);
WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
4);
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
PIPE_INTERLEAVE_SIZE, 0);
WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
}
}