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rtw88: 8723d: Add set_channel
Set MAC/BB/RF register according to specified channel. The function rtw_set_channel_mac() is used to set MAC registers, but 8723D only need some of them. For channel 14, we need to set different CCK DFIR values, so restore the values when channel 1 to 13 is selected. Spur calibration is needed in channel 13 and 14, and we do notch if spur is over threshold. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200504105010.10780-4-yhchuang@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
parent
158441a2be
commit
5f028a9cf4
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@ -40,6 +40,9 @@ void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw,
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}
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rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32);
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if (rtw_chip_wcpu_11n(rtwdev))
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return;
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value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL);
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value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
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rtw_write32(rtwdev, REG_AFE_CTRL1, value32);
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@ -287,6 +287,166 @@ static void rtw8723d_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
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rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
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}
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static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev,
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u8 channel, u32 thres)
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{
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u32 freq;
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bool ret = false;
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if (channel == 13)
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freq = FREQ_CH13;
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else if (channel == 14)
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freq = FREQ_CH14;
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else
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return false;
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rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE);
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rtw_write32(rtwdev, REG_PSDFN, freq);
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rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq);
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msleep(30);
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if (rtw_read32(rtwdev, REG_PSDRPT) >= thres)
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ret = true;
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rtw_write32(rtwdev, REG_PSDFN, freq);
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rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE);
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return ret;
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}
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static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch)
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{
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if (!notch) {
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rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
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rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
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rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
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rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
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rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
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rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
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rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
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return;
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}
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switch (channel) {
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case 13:
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rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
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rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
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rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000);
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rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
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rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
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rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
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rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
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break;
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case 14:
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rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);
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rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
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rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
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rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
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rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
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rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000);
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rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
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break;
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default:
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rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
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rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
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break;
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}
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}
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static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel)
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{
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bool notch;
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if (channel < 13) {
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rtw8723d_cfg_notch(rtwdev, channel, false);
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return;
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}
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notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES);
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rtw8723d_cfg_notch(rtwdev, channel, notch);
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}
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static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
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{
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u32 rf_cfgch_a, rf_cfgch_b;
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rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
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rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK);
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rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK;
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rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK;
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rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK);
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rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK);
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rf_cfgch_a &= ~RFCFGCH_BW_MASK;
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switch (bw) {
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case RTW_CHANNEL_WIDTH_20:
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rf_cfgch_a |= RFCFGCH_BW_20M;
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break;
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case RTW_CHANNEL_WIDTH_40:
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rf_cfgch_a |= RFCFGCH_BW_40M;
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break;
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default:
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break;
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}
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rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a);
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rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b);
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rtw8723d_spur_cal(rtwdev, channel);
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}
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static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR] = {
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[0] = {
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{ .len = 4, .reg = 0xA24, .val = 0x64B80C1C },
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{ .len = 4, .reg = 0xA28, .val = 0x00008810 },
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{ .len = 4, .reg = 0xAAC, .val = 0x01235667 },
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},
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[1] = {
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{ .len = 4, .reg = 0xA24, .val = 0x0000B81C },
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{ .len = 4, .reg = 0xA28, .val = 0x00000000 },
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{ .len = 4, .reg = 0xAAC, .val = 0x00003667 },
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},
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};
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static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
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u8 primary_ch_idx)
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{
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const struct rtw_backup_info *cck_dfir;
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int i;
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cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];
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for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++)
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rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val);
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switch (bw) {
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case RTW_CHANNEL_WIDTH_20:
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rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);
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rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);
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rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1);
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rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa);
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break;
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case RTW_CHANNEL_WIDTH_40:
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rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);
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rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);
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rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0);
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rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND,
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(primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
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break;
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default:
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break;
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}
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}
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static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
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u8 primary_chan_idx)
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{
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rtw8723d_set_channel_rf(rtwdev, channel, bw);
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rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
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rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
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}
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#define BIT_CFENDFORM BIT(9)
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#define BIT_WMAC_TCR_ERR0 BIT(12)
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#define BIT_WMAC_TCR_ERR1 BIT(13)
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@ -383,6 +543,7 @@ static struct rtw_chip_ops rtw8723d_ops = {
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.phy_set_param = rtw8723d_phy_set_param,
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.read_efuse = rtw8723d_read_efuse,
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.query_rx_desc = rtw8723d_query_rx_desc,
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.set_channel = rtw8723d_set_channel,
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.mac_init = rtw8723d_mac_init,
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.read_rf = rtw_phy_read_rf_sipi,
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.write_rf = rtw_phy_write_rf_reg_sipi,
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@ -66,7 +66,38 @@ struct rtw8723d_efuse {
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#define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
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#define SPUR_THRES 0x16
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#define CCK_DFIR_NR 3
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#define DIS_3WIRE 0xccf000c0
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#define EN_3WIRE 0xccc000c0
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#define START_PSD 0x400000
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#define FREQ_CH13 0xfccd
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#define FREQ_CH14 0xff9a
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#define RFCFGCH_CHANNEL_MASK GENMASK(7, 0)
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#define RFCFGCH_BW_MASK (BIT(11) | BIT(10))
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#define RFCFGCH_BW_20M (BIT(11) | BIT(10))
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#define RFCFGCH_BW_40M BIT(10)
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#define BIT_MASK_RFMOD BIT(0)
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#define REG_PSDFN 0x0808
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#define REG_ANALOG_P4 0x088c
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#define REG_PSDRPT 0x08b4
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#define REG_FPGA1_RFMOD 0x0900
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#define REG_BBRX_DFIR 0x0954
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#define BIT_MASK_RXBB_DFIR GENMASK(27, 24)
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#define BIT_RXBB_DFIR_EN BIT(19)
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#define REG_CCK0_SYS 0x0a00
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#define BIT_CCK_SIDE_BAND BIT(4)
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#define REG_OFDM0_RXDSP 0x0c40
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#define BIT_MASK_RXDSP GENMASK(28, 24)
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#define BIT_EN_RXDSP BIT(9)
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#define REG_OFDM0_XAAGC1 0x0c50
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#define REG_OFDM0_XBAGC1 0x0c58
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#define REG_OFDM1_CFOTRK 0x0d2c
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#define BIT_EN_CFOTRK BIT(28)
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#define REG_OFDM1_CSI1 0x0d40
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#define REG_OFDM1_CSI2 0x0d44
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#define REG_OFDM1_CSI3 0x0d48
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#define REG_OFDM1_CSI4 0x0d4c
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#endif
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