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drm/msm/a8xx: Add perfcntr flush sequence

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With the slice architecture, we need to flush the slice and unslice
counters to perf RAM before reading counters.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728216/
Message-ID: <20260526145137.160554-13-robin.clark@oss.qualcomm.com>
This commit is contained in:
Rob Clark 2026-05-26 07:50:46 -07:00
parent 5eedc8c2d0
commit 5ef26a2a4b
3 changed files with 22 additions and 0 deletions
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1
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
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@ -2843,6 +2843,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = {
.progress = a8xx_progress,
.sysprof_setup = a6xx_gmu_sysprof_setup,
.perfcntr_configure = a6xx_perfcntr_configure,
.perfcntr_flush = a8xx_perfcntr_flush,
},
.init = a6xx_gpu_init,
.get_timestamp = a8xx_gmu_get_timestamp,

1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
View File

@ -334,5 +334,6 @@ void a8xx_preempt_hw_init(struct msm_gpu *gpu);
void a8xx_preempt_trigger(struct msm_gpu *gpu);
void a8xx_preempt_irq(struct msm_gpu *gpu);
bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
void a8xx_perfcntr_flush(struct msm_gpu *gpu);
void a8xx_recover(struct msm_gpu *gpu);
#endif /* __A6XX_GPU_H__ */

20
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
View File

@ -1346,3 +1346,23 @@ bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{
return true;
}
void a8xx_perfcntr_flush(struct msm_gpu *gpu)
{
u32 val;
/*
* Flush delta counters (both perf counters and pipe stats) present in
* RBBM_S and RBBM_US to perf RAM logic to get the latest data.
*/
gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_CMD, BIT(0));
gpu_write(gpu, REG_A8XX_RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD, BIT(0));
/* Ensure all writes are posted before polling status register */
wmb();
if (gpu_poll_timeout(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_STATUS, val,
val & BIT(0), 100, 100 * 1000)) {
dev_err(&gpu->pdev->dev, "Perfcounter flush timed out: status=0x%08x\n", val);
}
}