github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-21 13:27:57 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

clk: qcom: gcc-msm8998: add SSC-related clocks

Browse Source 
Add four clocks which need to be manipulated in order to initialize the AHB
bus which exposes the SCC block in the global address space.

If a device is known to be configured such that writing to these
registers from Linux is not permitted, the 'protected-clocks'
device tree property must be used to denote that fact.

Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411072156.24451-3-michael.srba@seznam.cz
This commit is contained in:
Michael Srba 2022-04-11 09:21:53 +02:00 committed by Bjorn Andersson
parent ec5a164e08
commit 5ef1e4abc7
1 changed files with 56 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
drivers/clk/qcom/gcc-msm8998.c
View File

@ -2833,6 +2833,58 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
},
};
static struct clk_branch gcc_im_sleep_clk = {
.halt_reg = 0x4300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_im_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch aggre2_snoc_north_axi_clk = {
.halt_reg = 0x83010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x83010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "aggre2_snoc_north_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ssc_xo_clk = {
.halt_reg = 0x63018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x63018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "ssc_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ssc_cnoc_ahbs_clk = {
.halt_reg = 0x6300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "ssc_cnoc_ahbs_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.gds_hw_ctrl = 0x0,
@ -3036,6 +3088,10 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
[GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr,
[AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,
[SSC_XO] = &ssc_xo_clk.clkr,
[SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,
};
static struct gdsc *gcc_msm8998_gdscs[] = {