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arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts

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Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers.  Drop the masks.
While at it, replace the magic number for IRQ_TYPE_LEVEL_HIGH by its
symbolic definition.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/f9c6eddebebcd2e128edd2dbc51706e23589f9e8.1772643434.git.geert+renesas@glider.be
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
Geert Uytterhoeven 2026-03-04 18:10:58 +01:00 committed by Neil Armstrong
parent 028ef9c96e
commit 5ecee47dc9
1 changed files with 5 additions and 5 deletions
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10
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
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@ -53,10 +53,10 @@ pwrc: power-controller {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@ -84,7 +84,7 @@ gic: interrupt-controller@ff200000 {
interrupt-controller;
reg = <0x0 0xff200000 0 0x10000>,
<0x0 0xff240000 0 0x80000>;
interrupts = <GIC_PPI 9 0xf04>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
apb: bus@fe000000 {