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drm/i915/lt_phy: Add .enable_clock hook on DDI

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Enable PLL clock on DDI by moving part of the PLL enabling
sequence into a DDI clock enabling function.

v2: Reuse intel_mtl_pll_enable_clock for DDI clock enabling

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-17-mika.kahola@intel.com
This commit is contained in:
Mika Kahola 2026-03-12 08:06:49 +00:00
parent 27d911f87f
commit 5ec58d7149
4 changed files with 34 additions and 21 deletions
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2
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@ -5298,7 +5298,7 @@ void intel_ddi_init(struct intel_display *display,
encoder->pipe_mask = ~0;
if (HAS_LT_PHY(display)) {
encoder->enable_clock = intel_xe3plpd_pll_enable;
encoder->enable_clock = intel_mtl_pll_enable_clock;
encoder->disable_clock = intel_xe3plpd_pll_disable;
encoder->port_pll_type = intel_mtl_port_pll_type;
encoder->get_config = xe3plpd_ddi_get_config;

13
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
View File

@ -4595,7 +4595,20 @@ static int xe3plpd_pll_get_freq(struct intel_display *display,
return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
}
static void xe3plpd_pll_enable(struct intel_display *display,
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_encoder *encoder = get_intel_encoder(display, pll);
if (drm_WARN_ON(display->drm, !encoder))
return;
intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state);
}
static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
.enable = xe3plpd_pll_enable,
.get_hw_state = xe3plpd_pll_get_hw_state,
.get_freq = xe3plpd_pll_get_freq,
};

32
drivers/gpu/drm/i915/display/intel_lt_phy.c
View File

@ -1901,9 +1901,11 @@ intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
}
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_display *display = to_intel_display(encoder);
int port_clock = intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool lane_reversal = dig_port->lane_reversal;
u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
@ -1919,11 +1921,11 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
wakeref = intel_lt_phy_transaction_begin(encoder);
/* 1. Enable MacCLK at default 162 MHz frequency. */
intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
intel_lt_phy_lane_reset(encoder, dpll_hw_state->ltpll.lane_count);
/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state->dpll_hw_state.ltpll,
crtc_state->port_clock, lane_reversal);
intel_lt_phy_program_port_clock_ctl(encoder, &dpll_hw_state->ltpll,
port_clock, lane_reversal);
/* 3. Change owned PHY lanes power to Ready state. */
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
@ -1933,13 +1935,12 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
* 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
* encoded rate and encoded mode.
*/
if (intel_lt_phy_config_changed(encoder, &crtc_state->dpll_hw_state.ltpll,
crtc_state->port_clock)) {
if (intel_lt_phy_config_changed(encoder, &dpll_hw_state->ltpll, port_clock)) {
/*
* 5. Program the PHY internal PLL registers over PHY message bus for the desired
* frequency and protocol type
*/
intel_lt_phy_program_pll(encoder, &crtc_state->dpll_hw_state.ltpll);
intel_lt_phy_program_pll(encoder, &dpll_hw_state->ltpll);
/* 6. Use the P2P transaction flow */
/*
@ -1971,8 +1972,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
* Change. We handle this step in bxt_set_cdclk().
*/
/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
crtc_state->port_clock);
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
@ -2019,7 +2019,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
lane_phy_pulse_status,
lane_phy_pulse_status);
} else {
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
}
/*
@ -2030,7 +2030,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
XELPDP_P0_STATE_ACTIVE);
intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll);
intel_lt_phy_enable_disable_tx(encoder, &dpll_hw_state->ltpll);
intel_lt_phy_transaction_end(encoder, wakeref);
}
@ -2288,14 +2288,10 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
}
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
if (intel_tc_port_in_tbt_alt_mode(dig_port))
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
else
intel_lt_phy_pll_enable(encoder, crtc_state);
intel_lt_phy_pll_enable(encoder, pll, dpll_hw_state);
}
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)

8
drivers/gpu/drm/i915/display/intel_lt_phy.h
View File

@ -11,13 +11,16 @@
struct drm_printer;
struct intel_atomic_state;
struct intel_display;
struct intel_dpll;
struct intel_dpll_hw_state;
struct intel_encoder;
struct intel_crtc_state;
struct intel_crtc;
struct intel_lt_phy_pll_state;
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
void intel_lt_phy_pll_disable(struct intel_encoder *encoder);
int
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
@ -40,7 +43,8 @@ int
intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
u32 frequency_khz);
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
void intel_lt_phy_verify_plls(struct intel_display *display);