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arm64: dts: rockchip: Add GMAC nodes for RK3528

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Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.

Add device tree nodes for the two Ethernet controllers in RK3528.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250509202402.260038-2-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Jonas Karlman 2025-05-09 20:23:57 +00:00 committed by Heiko Stuebner
parent 376cb96962
commit 5eb28f461a
1 changed files with 105 additions and 0 deletions
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105
arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@ -677,6 +677,111 @@ saradc: adc@ffae0000 {
status = "disabled";
};
gmac0: ethernet@ffbd0000 {
compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xffbd0000 0x0 0x10000>;
clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
<&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
<&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
clock-names = "stmmaceth", "clk_mac_ref",
"mac_clk_rx", "mac_clk_tx",
"pclk_mac", "aclk_mac";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
phy-handle = <&rmii0_phy>;
phy-mode = "rmii";
resets = <&cru SRST_A_MAC_VO>;
reset-names = "stmmaceth";
rockchip,grf = <&vo_grf>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
snps,mixed-burst;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,tso;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
rmii0_phy: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x2>;
clocks = <&cru CLK_MACPHY>;
phy-is-integrated;
pinctrl-names = "default";
pinctrl-0 = <&fephym0_led_link>,
<&fephym0_led_spd>;
resets = <&cru SRST_MACPHY>;
};
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <8>;
snps,wr_osr_lmt = <4>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
};
gmac1: ethernet@ffbe0000 {
compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xffbe0000 0x0 0x10000>;
clocks = <&cru CLK_GMAC1_SRC_VPU>,
<&cru CLK_GMAC1_RMII_VPU>,
<&cru PCLK_MAC_VPU>,
<&cru ACLK_MAC_VPU>;
clock-names = "stmmaceth",
"clk_mac_ref",
"pclk_mac",
"aclk_mac";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
resets = <&cru SRST_A_MAC>;
reset-names = "stmmaceth";
rockchip,grf = <&vpu_grf>;
snps,axi-config = <&gmac1_stmmac_axi_setup>;
snps,mixed-burst;
snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
snps,tso;
status = "disabled";
mdio1: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
gmac1_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <8>;
snps,wr_osr_lmt = <4>;
};
gmac1_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
gmac1_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
};
sdhci: mmc@ffbf0000 {
compatible = "rockchip,rk3528-dwcmshc",
"rockchip,rk3588-dwcmshc";