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arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

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The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.

The CMN PLL driver did not account for the ref clock divider which is 2
for IPQ5018. Therefore, the computed rate was twice the actual output.

With the driver now accounting for the CMN PLL reference clock
divider (commit: 88c543fff7), set the correct reference clock rate.

Fixes: c006b249c5 ("arm64: dts: ipq5018: Add CMN PLL node")
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260521-ipq5018-cmn-pll-rate-fix-v2-1-04b28a92e0f2@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
George Moussalem 2026-05-21 11:55:58 +04:00 committed by Bjorn Andersson
parent cab6d9627e
commit 5e92312a1d
1 changed files with 1 additions and 1 deletions
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2
arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@ -256,7 +256,7 @@ cmn_pll: clock-controller@9b000 {
"sys";
#clock-cells = <1>;
assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
assigned-clock-rates-u64 = /bits/ 64 <4800000000>;
};
qfprom: qfprom@a0000 {