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wifi: rtw89: pci: consider RTL8922D in PCI common flow
Clear TX/RX ring index, PCI operating mode, SER setting, PCI LTR and preinit settings. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260110022019.2254969-9-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
parent
8e47ae0786
commit
5e632c7ca9
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@ -55,6 +55,8 @@
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#define B_AX_CALIB_EN BIT(13)
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#define B_AX_DIV GENMASK(15, 14)
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#define RAC_SET_PPR_V1 0x31
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#define RAC_ANA41 0x41
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#define PHY_ERR_FLAG_EN BIT(6)
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#define R_AX_DBI_FLAG 0x1090
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#define B_AX_DBI_RFLAG BIT(17)
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@ -145,6 +147,11 @@
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#define R_RAC_DIRECT_OFFSET_BE_LANE0_G2 0x3900
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#define R_RAC_DIRECT_OFFSET_BE_LANE1_G2 0x3980
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#define RAC_DIRECT_OFFESET_L0_G1 0x3800
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#define RAC_DIRECT_OFFESET_L1_G1 0x3900
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#define RAC_DIRECT_OFFESET_L0_G2 0x3A00
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#define RAC_DIRECT_OFFESET_L1_G2 0x3B00
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#define RTW89_PCI_WR_RETRY_CNT 20
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/* Interrupts */
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@ -296,6 +303,10 @@
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#define B_BE_PCIE_EN_AUX_CLK BIT(0)
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#define R_BE_PCIE_PS_CTRL 0x3008
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#define B_BE_ASPM_L11_EN BIT(19)
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#define B_BE_ASPM_L12_EN BIT(18)
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#define B_BE_PCIPM_L11_EN BIT(17)
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#define B_BE_PCIPM_L12_EN BIT(16)
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#define B_BE_RSM_L0S_EN BIT(8)
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#define B_BE_CMAC_EXIT_L1_EN BIT(7)
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#define B_BE_DMAC0_EXIT_L1_EN BIT(6)
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@ -949,6 +960,12 @@
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#define R_BE_PCIE_CRPWM 0x30C4
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#define R_BE_L1_2_CTRL_HCILDO 0x3110
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#define B_BE_PM_CLKREQ_EXT_RB BIT(11)
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#define B_BE_PCIE_DIS_RTK_PRST_N_L1_2 BIT(10)
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#define B_BE_PCIE_PRST_IN_L1_2_RB BIT(9)
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#define B_BE_PCIE_PRST_SEL_RB_V1 BIT(8)
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#define B_BE_PCIE_DIS_L2_CTRL_APHY_SUSB BIT(7)
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#define B_BE_PCIE_DIS_L1_2_CTRL_APHY_SUSB BIT(6)
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#define B_BE_PCIE_DIS_L1_2_CTRL_HCILDO BIT(0)
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#define R_BE_PL1_DBG_INFO 0x3120
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@ -998,9 +1015,11 @@
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#define B_BE_PL1_SER_PL1_EN BIT(31)
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#define B_BE_PL1_IGNORE_HOT_RST BIT(30)
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#define B_BE_PL1_TIMER_UNIT_MASK GENMASK(19, 17)
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#define PCIE_SER_TIMER_UNIT 0x2
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#define B_BE_PL1_TIMER_CLEAR BIT(0)
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#define R_BE_REG_PL1_MASK 0x34B0
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#define B_BE_SER_LTSSM_UNSTABLE_MASK BIT(6)
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#define B_BE_SER_PCLKREQ_ACK_MASK BIT(5)
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#define B_BE_SER_PM_CLK_MASK BIT(4)
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#define B_BE_SER_LTSSM_IMR BIT(3)
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@ -1030,6 +1049,18 @@
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#define B_BE_CLR_CH2_IDX BIT(2)
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#define B_BE_CLR_CH1_IDX BIT(1)
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#define B_BE_CLR_CH0_IDX BIT(0)
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#define B_BE_CLR_ALL_IDX_MASK (B_BE_CLR_CH0_IDX | B_BE_CLR_CH1_IDX | \
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B_BE_CLR_CH2_IDX | B_BE_CLR_CH3_IDX | \
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B_BE_CLR_CH4_IDX | B_BE_CLR_CH5_IDX | \
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B_BE_CLR_CH6_IDX | B_BE_CLR_CH7_IDX | \
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B_BE_CLR_CH8_IDX | B_BE_CLR_CH9_IDX | \
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B_BE_CLR_CH10_IDX | B_BE_CLR_CH11_IDX | \
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B_BE_CLR_CH12_IDX | B_BE_CLR_CH13_IDX | \
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B_BE_CLR_CH14_IDX)
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#define B_BE_CLR_ALL_IDX_MASK_V1 (B_BE_CLR_CH0_IDX | B_BE_CLR_CH2_IDX | \
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B_BE_CLR_CH4_IDX | B_BE_CLR_CH6_IDX | \
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B_BE_CLR_CH8_IDX | B_BE_CLR_CH10_IDX | \
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B_BE_CLR_CH12_IDX)
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#define R_BE_RXBD_RWPTR_CLR1_V1 0xB018
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#define B_BE_CLR_ROQ1_IDX_V1 BIT(5)
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@ -46,6 +46,14 @@ static void rtw89_pci_aspm_set_be(struct rtw89_dev *rtwdev, bool enable)
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static void rtw89_pci_l1ss_set_be(struct rtw89_dev *rtwdev, bool enable)
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{
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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struct rtw89_hal *hal = &rtwdev->hal;
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if (enable && chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)
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rtw89_write32_set(rtwdev, R_BE_PCIE_PS_CTRL,
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B_BE_ASPM_L11_EN | B_BE_ASPM_L12_EN |
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B_BE_PCIPM_L11_EN | B_BE_PCIPM_L12_EN);
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if (enable)
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rtw89_write32_set(rtwdev, R_BE_PCIE_MIX_CFG,
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B_BE_L1SUB_ENABLE);
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@ -154,7 +162,7 @@ static void rtw89_pci_ctrl_trxdma_pcie_be(struct rtw89_dev *rtwdev,
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rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
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if (io_en == MAC_AX_PCIE_ENABLE)
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if (io_en == MAC_AX_PCIE_ENABLE && rtwdev->chip->chip_id == RTL8922A)
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rtw89_write32_mask(rtwdev, R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1,
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B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK, 4);
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}
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@ -162,14 +170,15 @@ static void rtw89_pci_ctrl_trxdma_pcie_be(struct rtw89_dev *rtwdev,
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static void rtw89_pci_clr_idx_all_be(struct rtw89_dev *rtwdev)
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{
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struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_pci_rx_ring *rx_ring;
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u32 val;
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val = B_BE_CLR_CH0_IDX | B_BE_CLR_CH1_IDX | B_BE_CLR_CH2_IDX |
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B_BE_CLR_CH3_IDX | B_BE_CLR_CH4_IDX | B_BE_CLR_CH5_IDX |
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B_BE_CLR_CH6_IDX | B_BE_CLR_CH7_IDX | B_BE_CLR_CH8_IDX |
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B_BE_CLR_CH9_IDX | B_BE_CLR_CH10_IDX | B_BE_CLR_CH11_IDX |
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B_BE_CLR_CH12_IDX | B_BE_CLR_CH13_IDX | B_BE_CLR_CH14_IDX;
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if (chip->chip_id == RTL8922A)
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val = B_BE_CLR_ALL_IDX_MASK;
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else
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val = B_BE_CLR_ALL_IDX_MASK_V1;
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rtw89_write32(rtwdev, R_BE_TXBD_RWPTR_CLR1, val);
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rtw89_write32(rtwdev, R_BE_RXBD_RWPTR_CLR1_V1,
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@ -226,20 +235,24 @@ static int rtw89_pci_poll_dma_all_idle_be(struct rtw89_dev *rtwdev)
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static void rtw89_pci_mode_op_be(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_pci_info *info = rtwdev->pci_info;
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const struct rtw89_chip_info *chip = rtwdev->chip;
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u32 val32_init1, val32_rxapp, val32_exp;
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val32_init1 = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
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val32_rxapp = rtw89_read32(rtwdev, R_BE_RX_APPEND_MODE);
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if (chip->chip_id == RTL8922A)
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val32_rxapp = rtw89_read32(rtwdev, R_BE_RX_APPEND_MODE);
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val32_exp = rtw89_read32(rtwdev, R_BE_HAXI_EXP_CTRL_V1);
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if (info->rxbd_mode == MAC_AX_RXBD_PKT) {
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val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_NORM,
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B_BE_RXQ_RXBD_MODE_MASK);
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} else if (info->rxbd_mode == MAC_AX_RXBD_SEP) {
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val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_SEP,
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B_BE_RXQ_RXBD_MODE_MASK);
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val32_rxapp = u32_replace_bits(val32_rxapp, 0,
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B_BE_APPEND_LEN_MASK);
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if (chip->chip_id == RTL8922A) {
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if (info->rxbd_mode == MAC_AX_RXBD_PKT) {
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val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_NORM,
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B_BE_RXQ_RXBD_MODE_MASK);
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} else if (info->rxbd_mode == MAC_AX_RXBD_SEP) {
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val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_SEP,
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B_BE_RXQ_RXBD_MODE_MASK);
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val32_rxapp = u32_replace_bits(val32_rxapp, 0,
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B_BE_APPEND_LEN_MASK);
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}
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}
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val32_init1 = u32_replace_bits(val32_init1, info->tx_burst,
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@ -254,7 +267,8 @@ static void rtw89_pci_mode_op_be(struct rtw89_dev *rtwdev)
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B_BE_CFG_WD_PERIOD_ACTIVE_MASK);
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rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val32_init1);
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rtw89_write32(rtwdev, R_BE_RX_APPEND_MODE, val32_rxapp);
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if (chip->chip_id == RTL8922A)
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rtw89_write32(rtwdev, R_BE_RX_APPEND_MODE, val32_rxapp);
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rtw89_write32(rtwdev, R_BE_HAXI_EXP_CTRL_V1, val32_exp);
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}
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@ -280,6 +294,10 @@ static void rtw89_pci_debounce_be(struct rtw89_dev *rtwdev)
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static void rtw89_pci_ldo_low_pwr_be(struct rtw89_dev *rtwdev)
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{
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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struct rtw89_hal *hal = &rtwdev->hal;
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u32 clr;
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rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_PSUS_OFF_CAPC_EN);
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rtw89_write32_set(rtwdev, R_BE_SYS_PAGE_CLK_GATED,
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B_BE_SOP_OFFPOOBS_PC | B_BE_CPHY_AUXCLK_OP |
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@ -287,7 +305,16 @@ static void rtw89_pci_ldo_low_pwr_be(struct rtw89_dev *rtwdev)
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rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN |
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B_BE_PCIE_DIS_L2_RTK_PERST |
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B_BE_PCIE_DIS_L2__CTRL_LDO_HCI);
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rtw89_write32_clr(rtwdev, R_BE_L1_2_CTRL_HCILDO, B_BE_PCIE_DIS_L1_2_CTRL_HCILDO);
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if (chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)
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clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO |
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B_BE_PCIE_DIS_L1_2_CTRL_APHY_SUSB |
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B_BE_PCIE_DIS_RTK_PRST_N_L1_2 |
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B_BE_PCIE_DIS_L2_CTRL_APHY_SUSB;
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else
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clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO;
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rtw89_write32_clr(rtwdev, R_BE_L1_2_CTRL_HCILDO, clr);
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}
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static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev)
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@ -303,11 +330,25 @@ static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev)
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rtw89_write32_set(rtwdev, R_BE_EFUSE_CTRL_2_V1, B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL);
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rtw89_write32_set(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_SYM_AUX_CLK_SEL);
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if (chip->chip_id != RTL8922D)
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return;
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rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_SYM_PRST_CPHY_RST);
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rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_USUS_OFFCAPC_EN);
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}
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static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
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{
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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struct rtw89_hal *hal = &rtwdev->hal;
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u32 val32;
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int ret;
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if (chip_id == RTL8922D)
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goto be2_chips;
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else if (chip_id != RTL8922A)
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return;
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rtw89_write32(rtwdev, R_BE_PL1_DBG_INFO, 0x0);
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rtw89_write32_set(rtwdev, R_BE_FWS1IMR, B_BE_PCIE_SER_TIMEOUT_INDIC_EN);
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@ -318,6 +359,43 @@ static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
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val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR |
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B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK;
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rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
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return;
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be2_chips:
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rtw89_write32_clr(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
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rtw89_write32_set(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
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rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
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RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
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rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
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RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
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rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
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RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
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rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
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RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
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val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
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val32 &= ~B_BE_PL1_SER_PL1_EN;
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rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
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ret = read_poll_timeout_atomic(rtw89_read32, val32, !val32,
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1, 1000, false, rtwdev, R_BE_REG_PL1_ISR);
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if (ret)
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rtw89_warn(rtwdev, "[ERR] PCIE SER clear poll fail\n");
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val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
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val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR |
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B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK |
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B_BE_SER_LTSSM_UNSTABLE_MASK;
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rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
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rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK,
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PCIE_SER_TIMER_UNIT);
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rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
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if (hal->cid == RTL8922D_CID7090)
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rtw89_write32_set(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_SER_DETECT_EN);
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}
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static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool enable)
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@ -416,6 +494,7 @@ static int rtw89_pci_ops_mac_pre_deinit_be(struct rtw89_dev *rtwdev)
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int rtw89_pci_ltr_set_v2(struct rtw89_dev *rtwdev, bool en)
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{
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u32 ctrl0, cfg0, cfg1, dec_ctrl, idle_ltcy, act_ltcy, dis_ltcy;
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u32 ltr_idle_lat_ctrl, ltr_act_lat_ctrl;
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ctrl0 = rtw89_read32(rtwdev, R_BE_LTR_CTRL_0);
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if (rtw89_pci_ltr_is_err_reg_val(ctrl0))
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@ -458,8 +537,16 @@ int rtw89_pci_ltr_set_v2(struct rtw89_dev *rtwdev, bool en)
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cfg0 = u32_replace_bits(cfg0, 3, B_BE_LTR_IDX_IDLE_MASK);
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dec_ctrl = u32_replace_bits(dec_ctrl, 0, B_BE_LTR_IDX_DISABLE_V1_MASK);
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rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1, 0x90039003);
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rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1, 0x880b880b);
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if (rtwdev->chip->chip_id == RTL8922A) {
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ltr_idle_lat_ctrl = 0x90039003;
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ltr_act_lat_ctrl = 0x880b880b;
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} else {
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ltr_idle_lat_ctrl = 0x90019001;
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ltr_act_lat_ctrl = 0x88018801;
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}
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rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1, ltr_idle_lat_ctrl);
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rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1, ltr_act_lat_ctrl);
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rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX0_V1, 0);
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rtw89_write32(rtwdev, R_BE_LTR_DECISION_CTRL_V1, dec_ctrl);
|
||||
rtw89_write32(rtwdev, R_BE_LTR_CFG_0, cfg0);
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||||
|
|
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|||
|
|
@ -3831,6 +3831,7 @@
|
|||
#define B_BE_EN_WLON BIT(16)
|
||||
#define B_BE_APDM_HPDN BIT(15)
|
||||
#define B_BE_PSUS_OFF_CAPC_EN BIT(14)
|
||||
#define B_BE_USUS_OFFCAPC_EN BIT(13)
|
||||
#define B_BE_AFSM_PCIE_SUS_EN BIT(12)
|
||||
#define B_BE_AFSM_WLSUS_EN BIT(11)
|
||||
#define B_BE_APFM_SWLPS BIT(10)
|
||||
|
|
@ -3899,6 +3900,8 @@
|
|||
#define B_BE_SYM_PADPDN_WL_RFC0_1P3 BIT(5)
|
||||
|
||||
#define R_BE_RSV_CTRL 0x001C
|
||||
#define B_BE_R_SYM_PRST_CPHY_RST BIT(25)
|
||||
#define B_BE_R_SYM_PRST_PDN_EN BIT(24)
|
||||
#define B_BE_HR_BE_DBG GENMASK(23, 12)
|
||||
#define B_BE_R_SYM_DIS_PCIE_FLR BIT(9)
|
||||
#define B_BE_R_EN_HRST_PWRON BIT(8)
|
||||
|
|
@ -4038,6 +4041,7 @@
|
|||
|
||||
#define R_BE_SYS_SDIO_CTRL 0x0070
|
||||
#define B_BE_MCM_FLASH_EN BIT(28)
|
||||
#define B_BE_SER_DETECT_EN BIT(26)
|
||||
#define B_BE_PCIE_SEC_LOAD BIT(26)
|
||||
#define B_BE_PCIE_SER_RSTB BIT(25)
|
||||
#define B_BE_PCIE_SEC_LOAD_CLR BIT(24)
|
||||
|
|
@ -4497,6 +4501,16 @@
|
|||
#define B_BE_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
|
||||
#define B_BE_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
|
||||
|
||||
#define R_BE_PCIE_SER_DBG 0x02FC
|
||||
#define B_BE_PCIE_SER_DBG_MASK GENMASK(31, 10)
|
||||
#define B_BE_PCIE_SER_PHY_PROTECT BIT(9)
|
||||
#define B_BE_PCIE_SER_MAC_PROTECT BIT(8)
|
||||
#define B_BE_PCIE_SER_FLUSH_RSTB BIT(4)
|
||||
#define B_BE_PCIE_AXI_BRG_FLUSH_EN BIT(3)
|
||||
#define B_BE_PCIE_SER_AUXCLK_RDY BIT(2)
|
||||
#define B_BE_PCIE_SER_FRZ_REG_RST BIT(1)
|
||||
#define B_BE_PCIE_SER_FRZ_CFG_SPC_RST BIT(0)
|
||||
|
||||
#define R_BE_IC_PWR_STATE 0x03F0
|
||||
#define B_BE_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
|
||||
#define MAC_AX_SYS_ACT 0x220
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user