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arm64: dts: qcom: Remove sdm845-cheza boards
Cheza was a prototype board, used mainly by the ChromeOS folks, whose former efforts on making linux-arm-msm better we greatly appreciate. There are close to zero known-working devices at this point in time (see the link below) and it was never productized. Remove it to ease maintenance burden. Link: https://lore.kernel.org/linux-arm-msm/5567e441-055d-443a-b117-ec16b53dc059@oss.qualcomm.com/ Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250716-topic-goodnight_cheza-v2-1-6fa8d3261813@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Konrad Dybcio
Bjorn Andersson
parent
bc6776fab8
commit
5e4ca587f5
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@ -3109,7 +3109,6 @@ ARM/QUALCOMM CHROMEBOOK SUPPORT
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R: cros-qcom-dts-watchers@chromium.org
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F: arch/arm64/boot/dts/qcom/sc7180*
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F: arch/arm64/boot/dts/qcom/sc7280*
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F: arch/arm64/boot/dts/qcom/sdm845-cheza*
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ARM/QUALCOMM MAILING LIST
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L: linux-arm-msm@vger.kernel.org
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@ -232,9 +232,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
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sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
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@ -1,238 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Cheza board device tree source
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*
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* Copyright 2018 Google LLC.
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*/
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/dts-v1/;
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#include "sdm845-cheza.dtsi"
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/ {
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model = "Google Cheza (rev1)";
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compatible = "google,cheza-rev1", "qcom,sdm845";
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/*
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* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
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*/
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/*
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* NOTE: Technically pp3500_a is not the exact same signal as
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* pp3500_a_vbob (there's a load switch between them and the EC can
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* control pp3500_a via "en_pp3300_a"), but from the AP's point of
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* view they are the same.
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*/
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pp3500_a:
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pp3500_a_vbob: pp3500-a-vbob-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vreg_bob";
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/*
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* Comes on automatically when pp5000_ldo comes on, which
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* comes on automatically when ppvar_sys comes on
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*/
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3500000>;
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regulator-max-microvolt = <3500000>;
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vin-supply = <&ppvar_sys>;
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};
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pp3300_dx_edp: pp3300-dx-edp-regulator {
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/* Yes, it's really 3.5 despite the name of the signal */
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regulator-min-microvolt = <3500000>;
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regulator-max-microvolt = <3500000>;
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vin-supply = <&pp3500_a>;
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};
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};
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/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
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/*
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* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
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* that limits them to 3.0, and trying to run at 3.3V with that old firmware
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* prevents the system from booting.
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*/
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&src_pp3000_l19a {
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regulator-min-microvolt = <3008000>;
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regulator-max-microvolt = <3008000>;
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};
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&src_pp3300_l22a {
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/delete-property/regulator-boot-on;
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/delete-property/regulator-always-on;
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};
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&src_pp3300_l28a {
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regulator-min-microvolt = <3008000>;
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regulator-max-microvolt = <3008000>;
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};
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&src_vreg_bob {
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regulator-min-microvolt = <3500000>;
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regulator-max-microvolt = <3500000>;
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vin-supply = <&pp3500_a_vbob>;
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};
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/*
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* NON-REGULATOR OVERRIDES
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* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
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*/
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/* PINCTRL - board-specific pinctrl */
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&tlmm {
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gpio-line-names = "AP_SPI_FP_MISO",
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"AP_SPI_FP_MOSI",
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"AP_SPI_FP_CLK",
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"AP_SPI_FP_CS_L",
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"UART_AP_TX_DBG_RX",
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"UART_DBG_TX_AP_RX",
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"",
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"FP_RST_L",
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"FCAM_EN",
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"",
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"EDP_BRIJ_IRQ",
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"EC_IN_RW_ODL",
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"",
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"RCAM_MCLK",
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"FCAM_MCLK",
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"",
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"RCAM_EN",
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"CCI0_SDA",
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"CCI0_SCL",
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"CCI1_SDA",
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"CCI1_SCL",
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"FCAM_RST_L",
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"",
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"PEN_RST_L",
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"PEN_IRQ_L",
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"",
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"RCAM_VSYNC",
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"ESIM_MISO",
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"ESIM_MOSI",
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"ESIM_CLK",
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"ESIM_CS_L",
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"AP_PEN_1V8_SDA",
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"AP_PEN_1V8_SCL",
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"AP_TS_I2C_SDA",
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"AP_TS_I2C_SCL",
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"RCAM_RST_L",
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"",
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"AP_EDP_BKLTEN",
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"AP_BRD_ID1",
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"BOOT_CONFIG_4",
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"AMP_IRQ_L",
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"EDP_BRIJ_I2C_SDA",
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"EDP_BRIJ_I2C_SCL",
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"EN_PP3300_DX_EDP",
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"SD_CD_ODL",
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"BT_UART_RTS",
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"BT_UART_CTS",
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"BT_UART_RXD",
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"BT_UART_TXD",
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"AMP_I2C_SDA",
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"AMP_I2C_SCL",
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"AP_BRD_ID3",
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"",
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"AP_EC_SPI_CLK",
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"AP_EC_SPI_CS_L",
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"AP_EC_SPI_MISO",
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"AP_EC_SPI_MOSI",
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"FORCED_USB_BOOT",
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"AMP_BCLK",
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"AMP_LRCLK",
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"AMP_DOUT",
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"AMP_DIN",
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"AP_BRD_ID2",
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"PEN_PDCT_L",
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"HP_MCLK",
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"HP_BCLK",
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"HP_LRCLK",
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"HP_DOUT",
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"HP_DIN",
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"",
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"",
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"",
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"",
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"BT_SLIMBUS_DATA",
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"BT_SLIMBUS_CLK",
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"AMP_RESET_L",
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"",
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"FCAM_VSYNC",
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"",
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"AP_SKU_ID1",
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"EC_WOV_BCLK",
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"EC_WOV_LRCLK",
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"EC_WOV_DOUT",
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"",
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"",
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"AP_H1_SPI_MISO",
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"AP_H1_SPI_MOSI",
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"AP_H1_SPI_CLK",
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"AP_H1_SPI_CS_L",
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"",
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"AP_SPI_CS0_L",
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"AP_SPI_MOSI",
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"AP_SPI_MISO",
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"",
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"",
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"AP_SPI_CLK",
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"",
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"RFFE6_CLK",
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"RFFE6_DATA",
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"BOOT_CONFIG_1",
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"BOOT_CONFIG_2",
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"BOOT_CONFIG_0",
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"EDP_BRIJ_EN",
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"",
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"USB_HS_TX_EN",
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"UIM2_DATA",
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"UIM2_CLK",
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"UIM2_RST",
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"UIM2_PRESENT",
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"UIM1_DATA",
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"UIM1_CLK",
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"UIM1_RST",
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"",
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"AP_SKU_ID2",
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"SDM_GRFC_8",
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"SDM_GRFC_9",
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"AP_RST_REQ",
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"HP_IRQ",
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"TS_RESET_L",
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"PEN_EJECT_ODL",
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"HUB_RST_L",
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"FP_TO_AP_IRQ",
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"AP_EC_INT_L",
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"",
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"",
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"TS_INT_L",
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"AP_SUSPEND_L",
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"SDM_GRFC_3",
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"",
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"H1_AP_INT_ODL",
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"QLINK_REQ",
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"QLINK_EN",
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"SDM_GRFC_2",
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"BOOT_CONFIG_3",
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"WMSS_RESET_L",
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"SDM_GRFC_0",
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"SDM_GRFC_1",
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"RFFE3_DATA",
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"RFFE3_CLK",
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"RFFE4_DATA",
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"RFFE4_CLK",
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"RFFE5_DATA",
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"RFFE5_CLK",
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"GNSS_EN",
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"WCI2_LTE_COEX_RXD",
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"WCI2_LTE_COEX_TXD",
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"AP_RAM_ID1",
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"AP_RAM_ID2",
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"RFFE1_DATA",
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"RFFE1_CLK";
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};
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@ -1,238 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Cheza board device tree source
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*
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* Copyright 2018 Google LLC.
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*/
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/dts-v1/;
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#include "sdm845-cheza.dtsi"
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/ {
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model = "Google Cheza (rev2)";
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compatible = "google,cheza-rev2", "qcom,sdm845";
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/*
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* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
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*/
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/*
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* NOTE: Technically pp3500_a is not the exact same signal as
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* pp3500_a_vbob (there's a load switch between them and the EC can
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* control pp3500_a via "en_pp3300_a"), but from the AP's point of
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* view they are the same.
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*/
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pp3500_a:
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pp3500_a_vbob: pp3500-a-vbob-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vreg_bob";
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/*
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* Comes on automatically when pp5000_ldo comes on, which
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* comes on automatically when ppvar_sys comes on
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*/
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3500000>;
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regulator-max-microvolt = <3500000>;
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vin-supply = <&ppvar_sys>;
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};
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pp3300_dx_edp: pp3300-dx-edp-regulator {
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/* Yes, it's really 3.5 despite the name of the signal */
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regulator-min-microvolt = <3500000>;
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regulator-max-microvolt = <3500000>;
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vin-supply = <&pp3500_a>;
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};
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};
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/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
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/*
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* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
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* that limits them to 3.0, and trying to run at 3.3V with that old firmware
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* prevents the system from booting.
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*/
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&src_pp3000_l19a {
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regulator-min-microvolt = <3008000>;
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regulator-max-microvolt = <3008000>;
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};
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&src_pp3300_l22a {
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/delete-property/regulator-boot-on;
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/delete-property/regulator-always-on;
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};
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&src_pp3300_l28a {
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regulator-min-microvolt = <3008000>;
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regulator-max-microvolt = <3008000>;
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};
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&src_vreg_bob {
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regulator-min-microvolt = <3500000>;
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regulator-max-microvolt = <3500000>;
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vin-supply = <&pp3500_a_vbob>;
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};
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/*
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* NON-REGULATOR OVERRIDES
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* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
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*/
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/* PINCTRL - board-specific pinctrl */
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&tlmm {
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gpio-line-names = "AP_SPI_FP_MISO",
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"AP_SPI_FP_MOSI",
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"AP_SPI_FP_CLK",
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"AP_SPI_FP_CS_L",
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"UART_AP_TX_DBG_RX",
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"UART_DBG_TX_AP_RX",
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"BRIJ_SUSPEND",
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"FP_RST_L",
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"FCAM_EN",
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"",
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"EDP_BRIJ_IRQ",
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"EC_IN_RW_ODL",
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"",
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"RCAM_MCLK",
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"FCAM_MCLK",
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"",
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"RCAM_EN",
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"CCI0_SDA",
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"CCI0_SCL",
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"CCI1_SDA",
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"CCI1_SCL",
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"FCAM_RST_L",
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"FPMCU_BOOT0",
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"PEN_RST_L",
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"PEN_IRQ_L",
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"FPMCU_SEL_OD",
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"RCAM_VSYNC",
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"ESIM_MISO",
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"ESIM_MOSI",
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"ESIM_CLK",
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"ESIM_CS_L",
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"AP_PEN_1V8_SDA",
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"AP_PEN_1V8_SCL",
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"AP_TS_I2C_SDA",
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"AP_TS_I2C_SCL",
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"RCAM_RST_L",
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"",
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"AP_EDP_BKLTEN",
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"AP_BRD_ID1",
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"BOOT_CONFIG_4",
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"AMP_IRQ_L",
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"EDP_BRIJ_I2C_SDA",
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"EDP_BRIJ_I2C_SCL",
|
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"EN_PP3300_DX_EDP",
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"SD_CD_ODL",
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"BT_UART_RTS",
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"BT_UART_CTS",
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"BT_UART_RXD",
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"BT_UART_TXD",
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"AMP_I2C_SDA",
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"AMP_I2C_SCL",
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"AP_BRD_ID3",
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"",
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"AP_EC_SPI_CLK",
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"AP_EC_SPI_CS_L",
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"AP_EC_SPI_MISO",
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"AP_EC_SPI_MOSI",
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"FORCED_USB_BOOT",
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"AMP_BCLK",
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"AMP_LRCLK",
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"AMP_DOUT",
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"AMP_DIN",
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"AP_BRD_ID2",
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"PEN_PDCT_L",
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"HP_MCLK",
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"HP_BCLK",
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"HP_LRCLK",
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"HP_DOUT",
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"HP_DIN",
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"",
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"",
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"",
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"",
|
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"BT_SLIMBUS_DATA",
|
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"BT_SLIMBUS_CLK",
|
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"AMP_RESET_L",
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"",
|
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"FCAM_VSYNC",
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"",
|
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"AP_SKU_ID1",
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"EC_WOV_BCLK",
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"EC_WOV_LRCLK",
|
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"EC_WOV_DOUT",
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"",
|
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"",
|
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"AP_H1_SPI_MISO",
|
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"AP_H1_SPI_MOSI",
|
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"AP_H1_SPI_CLK",
|
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"AP_H1_SPI_CS_L",
|
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"",
|
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"AP_SPI_CS0_L",
|
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"AP_SPI_MOSI",
|
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"AP_SPI_MISO",
|
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"",
|
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"",
|
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"AP_SPI_CLK",
|
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"",
|
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"RFFE6_CLK",
|
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"RFFE6_DATA",
|
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"BOOT_CONFIG_1",
|
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"BOOT_CONFIG_2",
|
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"BOOT_CONFIG_0",
|
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"EDP_BRIJ_EN",
|
||||
"",
|
||||
"USB_HS_TX_EN",
|
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"UIM2_DATA",
|
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"UIM2_CLK",
|
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"UIM2_RST",
|
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"UIM2_PRESENT",
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"UIM1_DATA",
|
||||
"UIM1_CLK",
|
||||
"UIM1_RST",
|
||||
"",
|
||||
"AP_SKU_ID2",
|
||||
"SDM_GRFC_8",
|
||||
"SDM_GRFC_9",
|
||||
"AP_RST_REQ",
|
||||
"HP_IRQ",
|
||||
"TS_RESET_L",
|
||||
"PEN_EJECT_ODL",
|
||||
"HUB_RST_L",
|
||||
"FP_TO_AP_IRQ",
|
||||
"AP_EC_INT_L",
|
||||
"",
|
||||
"",
|
||||
"TS_INT_L",
|
||||
"AP_SUSPEND_L",
|
||||
"SDM_GRFC_3",
|
||||
"",
|
||||
"H1_AP_INT_ODL",
|
||||
"QLINK_REQ",
|
||||
"QLINK_EN",
|
||||
"SDM_GRFC_2",
|
||||
"BOOT_CONFIG_3",
|
||||
"WMSS_RESET_L",
|
||||
"SDM_GRFC_0",
|
||||
"SDM_GRFC_1",
|
||||
"RFFE3_DATA",
|
||||
"RFFE3_CLK",
|
||||
"RFFE4_DATA",
|
||||
"RFFE4_CLK",
|
||||
"RFFE5_DATA",
|
||||
"RFFE5_CLK",
|
||||
"GNSS_EN",
|
||||
"WCI2_LTE_COEX_RXD",
|
||||
"WCI2_LTE_COEX_TXD",
|
||||
"AP_RAM_ID1",
|
||||
"AP_RAM_ID2",
|
||||
"RFFE1_DATA",
|
||||
"RFFE1_CLK";
|
||||
};
|
||||
|
|
@ -1,174 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Cheza board device tree source
|
||||
*
|
||||
* Copyright 2018 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdm845-cheza.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Cheza (rev3+)";
|
||||
compatible = "google,cheza", "qcom,sdm845";
|
||||
};
|
||||
|
||||
/* PINCTRL - board-specific pinctrl */
|
||||
|
||||
&tlmm {
|
||||
gpio-line-names = "AP_SPI_FP_MISO",
|
||||
"AP_SPI_FP_MOSI",
|
||||
"AP_SPI_FP_CLK",
|
||||
"AP_SPI_FP_CS_L",
|
||||
"UART_AP_TX_DBG_RX",
|
||||
"UART_DBG_TX_AP_RX",
|
||||
"BRIJ_SUSPEND",
|
||||
"FP_RST_L",
|
||||
"FCAM_EN",
|
||||
"",
|
||||
"EDP_BRIJ_IRQ",
|
||||
"EC_IN_RW_ODL",
|
||||
"",
|
||||
"RCAM_MCLK",
|
||||
"FCAM_MCLK",
|
||||
"",
|
||||
"RCAM_EN",
|
||||
"CCI0_SDA",
|
||||
"CCI0_SCL",
|
||||
"CCI1_SDA",
|
||||
"CCI1_SCL",
|
||||
"FCAM_RST_L",
|
||||
"FPMCU_BOOT0",
|
||||
"PEN_RST_L",
|
||||
"PEN_IRQ_L",
|
||||
"FPMCU_SEL_OD",
|
||||
"RCAM_VSYNC",
|
||||
"ESIM_MISO",
|
||||
"ESIM_MOSI",
|
||||
"ESIM_CLK",
|
||||
"ESIM_CS_L",
|
||||
"AP_PEN_1V8_SDA",
|
||||
"AP_PEN_1V8_SCL",
|
||||
"AP_TS_I2C_SDA",
|
||||
"AP_TS_I2C_SCL",
|
||||
"RCAM_RST_L",
|
||||
"",
|
||||
"AP_EDP_BKLTEN",
|
||||
"AP_BRD_ID0",
|
||||
"BOOT_CONFIG_4",
|
||||
"AMP_IRQ_L",
|
||||
"EDP_BRIJ_I2C_SDA",
|
||||
"EDP_BRIJ_I2C_SCL",
|
||||
"EN_PP3300_DX_EDP",
|
||||
"SD_CD_ODL",
|
||||
"BT_UART_RTS",
|
||||
"BT_UART_CTS",
|
||||
"BT_UART_RXD",
|
||||
"BT_UART_TXD",
|
||||
"AMP_I2C_SDA",
|
||||
"AMP_I2C_SCL",
|
||||
"AP_BRD_ID2",
|
||||
"",
|
||||
"AP_EC_SPI_CLK",
|
||||
"AP_EC_SPI_CS_L",
|
||||
"AP_EC_SPI_MISO",
|
||||
"AP_EC_SPI_MOSI",
|
||||
"FORCED_USB_BOOT",
|
||||
"AMP_BCLK",
|
||||
"AMP_LRCLK",
|
||||
"AMP_DOUT",
|
||||
"AMP_DIN",
|
||||
"AP_BRD_ID1",
|
||||
"PEN_PDCT_L",
|
||||
"HP_MCLK",
|
||||
"HP_BCLK",
|
||||
"HP_LRCLK",
|
||||
"HP_DOUT",
|
||||
"HP_DIN",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"BT_SLIMBUS_DATA",
|
||||
"BT_SLIMBUS_CLK",
|
||||
"AMP_RESET_L",
|
||||
"",
|
||||
"FCAM_VSYNC",
|
||||
"",
|
||||
"AP_SKU_ID0",
|
||||
"EC_WOV_BCLK",
|
||||
"EC_WOV_LRCLK",
|
||||
"EC_WOV_DOUT",
|
||||
"",
|
||||
"",
|
||||
"AP_H1_SPI_MISO",
|
||||
"AP_H1_SPI_MOSI",
|
||||
"AP_H1_SPI_CLK",
|
||||
"AP_H1_SPI_CS_L",
|
||||
"",
|
||||
"AP_SPI_CS0_L",
|
||||
"AP_SPI_MOSI",
|
||||
"AP_SPI_MISO",
|
||||
"",
|
||||
"",
|
||||
"AP_SPI_CLK",
|
||||
"",
|
||||
"RFFE6_CLK",
|
||||
"RFFE6_DATA",
|
||||
"BOOT_CONFIG_1",
|
||||
"BOOT_CONFIG_2",
|
||||
"BOOT_CONFIG_0",
|
||||
"EDP_BRIJ_EN",
|
||||
"",
|
||||
"USB_HS_TX_EN",
|
||||
"UIM2_DATA",
|
||||
"UIM2_CLK",
|
||||
"UIM2_RST",
|
||||
"UIM2_PRESENT",
|
||||
"UIM1_DATA",
|
||||
"UIM1_CLK",
|
||||
"UIM1_RST",
|
||||
"",
|
||||
"AP_SKU_ID1",
|
||||
"SDM_GRFC_8",
|
||||
"SDM_GRFC_9",
|
||||
"AP_RST_REQ",
|
||||
"HP_IRQ",
|
||||
"TS_RESET_L",
|
||||
"PEN_EJECT_ODL",
|
||||
"HUB_RST_L",
|
||||
"FP_TO_AP_IRQ",
|
||||
"AP_EC_INT_L",
|
||||
"",
|
||||
"",
|
||||
"TS_INT_L",
|
||||
"AP_SUSPEND_L",
|
||||
"SDM_GRFC_3",
|
||||
/*
|
||||
* AP_FLASH_WP_L is crossystem ABI. Rev3 schematics
|
||||
* call it BIOS_FLASH_WP_R_L.
|
||||
*/
|
||||
"AP_FLASH_WP_L",
|
||||
"H1_AP_INT_ODL",
|
||||
"QLINK_REQ",
|
||||
"QLINK_EN",
|
||||
"SDM_GRFC_2",
|
||||
"BOOT_CONFIG_3",
|
||||
"WMSS_RESET_L",
|
||||
"SDM_GRFC_0",
|
||||
"SDM_GRFC_1",
|
||||
"RFFE3_DATA",
|
||||
"RFFE3_CLK",
|
||||
"RFFE4_DATA",
|
||||
"RFFE4_CLK",
|
||||
"RFFE5_DATA",
|
||||
"RFFE5_CLK",
|
||||
"GNSS_EN",
|
||||
"WCI2_LTE_COEX_RXD",
|
||||
"WCI2_LTE_COEX_TXD",
|
||||
"AP_RAM_ID0",
|
||||
"AP_RAM_ID1",
|
||||
"RFFE1_DATA",
|
||||
"RFFE1_CLK";
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user